Intel Xscale® Microarchitecture Implementation Options; Coprocessor 7 Register 4 - Psfs Bit; Block Diagram - Intel PXA255 Developer's Manual

System Architecture
Figure 2-1. Block Diagram
2.2 Intel XScale® Microarchitecture Implementation
Options
The processor incorporates the Intel XScale® microarchitecture which is described in a separate
document. This core contains implementation options which an Application Specific Standard
Product (ASSP) may elect to implement or omit. This section describes those options.
Most of these options are specified within the coprocessor register space. The processor does not
implement any coprocessor registers beyond those defined in the Intel XScale® microarchitecture.
The coprocessor registers which are ASSP specific, as stated in the Intel XScale®
Microarchitecture for the Intel® PXA255 Processor User's Manual, order number 278793, are
defined in the following sections.
2.2.1

Coprocessor 7 Register 4 - PSFS Bit

Bit 5 of this register is defined as the Power Source Fault Status bit or PSFS bit. This bit is set when
either nVDD_FAULT or nBATT_FAULT pins are asserted and the Imprecise Data Abort Enable
(IDAE) bit in the Power Manager Control Register (PMCR) is set.
This is a read-only register. Ignore reads from reserved bits.
2-2
RTC
OS Timer
PWM(2)
Int.
Controller
Clocks &
Power Man.
2
I S
2
I C
AC97
UARTs
NSSP
Microarchitecture
Slow IrDA
Fast IrDA
SSP
USB
Client
MMC
Color or
Grayscale
Memory
LCD
Controller
Controller
Variable
Latency I/O
Control
System Bus
PCMCIA
& CF
Control
Dynamic
Memory
Control
Intelfi XScale
Static
Memory
Control
3.6864 32.768
MHz KHz
Osc Osc
Intel® PXA255 Processor Developer's Manual
ASIC
Socket 0
XCVR
Socket 1
SDRAM/
SMROM
4 banks
ROM/
Flash/
SRAM
4 banks