Udccs4/9/14 Bit Definitions - Intel PXA255 Developer's Manual

Table 12-18. UDCCS4/9/14 Bit Definitions
0x 4060_0020
0x 4060_0034
0x4060_0048
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset x x x x x x
Bits Name
31:8
7 RSP
6 RNE
5:4
3 DME
2 ROF
1 RPC
0
12.6.7.1 Receive FIFO Service (RFS)
The receive FIFO service bit is set if the receive FIFO has one complete data packet in it and the
packet has been error checked by the UDC. A complete packet may be 256 bytes, a short packet, or
a zero packet. UDCCSx[RFS] is not cleared until all data is read from both buffers.
12.6.7.2 Receive Packet Complete (RPC)
The receive packet complete bit gets set by the UDC when an OUT packet is received. When this
bit is set, the IRx bit in the appropriate UDC status/interrupt register is set if receive interrupts are
enabled. This bit can be used to validate the other status/error bits in the endpoint(x) control/status
register. The UDCCSx[RPC] bit is cleared by writing a 1 to it.
12.6.7.3 Receive Overflow (ROF)
The receive overflow bit generates an interrupt on IRx in the appropriate UDC status/interrupt
register to alert the software that Isochronous data packets are being dropped because neither FIFO
buffer has room for them. This bit is cleared by writing a 1 to it.
Intel® PXA255 Processor Developer's Manual
reserved
x x x x x x x
— reserved
Receive short packet (read-only)
1 = Short packet received and ready for reading.
Receive FIFO not empty (read-only).
0 = Receive FIFO empty.
1 = Receive FIFO not empty.
— reserved
DMA Enable(read/write)
0 = Send receive interrupt after EOP receive
1 = Send data received interrupt after EOP received and Receive FIFO has < 32 bytes of
data
Receive overflow (read/write 1 to clear)
1 = Isochronous data packets are being dropped from the host because the receiver is full.
Receive packet complete (read/write 1 to clear).
0 = Error/status bits invalid.
1 = Receive packet has been received and error/status bits are valid.
Receive FIFO service (read-only).
RFS
0 = Receive FIFO has less than 1 data packet.
1 = Receive FIFO has 1 or more data packets.
UDCCS4
UDCCS9
UDCCS14
x x x x x x x x
Description
USB Device Controller
USB Device Controller
8 7 6 5 4 3
x x x 0 0 0 0 0
2 1 0
0 0 0
12-33