Isar Bit Definitions - Intel PXA255 Developer's Manual

Table 9-11. ISR Bit Definitions (Sheet 2 of 2)
Physical Address
4030_1698
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
1 ACKNAK
0 RWM
2
9.9.5 I C Slave Address Register (ISAR)
The ISAR, shown in
the processor responds when the 7-bit address matches the value in this register. The processor
writes this register before it enables I
assigned to the I
peripherals in the system. If the processor is reset, the ISAR is not affected. The ISAR register
default value is 0000000
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 9-12. ISAR Bit Definitions
Physical Address
4030_16A0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
31:7
6:0
Intel® PXA255 Processor Developer's Manual
2
I C Status Register
reserved
0 0 0 0 0 0 0
ACK/NAK Status:
2
0 = I C unit received or sent an ACK on the bus.
2
1 = I C unit received or sent a NAK.
Used in slave-transmit mode to determine when the transferred byte is the last one.
Updated after each byte and ACK/NAK information is received.
Read/Write Mode:
2
0 = I C unit is in master-transmit or slave-receive mode.
2
1 = I C unit is in master-receive or slave-transmit mode.
R/nW bit of the slave address. Automatically cleared by hardware after a stop state.
Table 9-12, defines the I
2
C unit) so it can be set to a value other than those of hard-wired I
.
2
2
I C Slave Address Register
reserved
0 0 0 0 0 0 0
— reserved
2
I C Slave Address: 7-bit address that the I
ISA
mode.
0 0 0 0 0 0 0 0
2
C unit's 7-bit slave address. In slave-receive mode,
2
C operations. The ISAR is fully programmable (no address is
0 0 0 0 0 0 0 0
2
C unit responds to when in slave-receive
2
I C Bus Interface Unit
2
I C Bus Interface Unit
8 7 6 5 4 3
0 0 0 0 0 0 0 0
2
C slave
2
I C Bus Interface Unit
8 7 6 5 4 3
ISA
0 0 0 0 0 0 0 0
2 1 0
0 0 0
2 1 0
0 0 0
9-27