Intel PXA255 Developer's Manual page 7

7.2.1 Enabling the Controller .........................................................................................7-4
7.2.2 Disabling the Controller ........................................................................................7-5
7.2.3 Resetting the Controller ........................................................................................7-5
7.3 Detailed Module Descriptions ............................................................................................7-5
7.3.1 Input FIFOs ...........................................................................................................7-5
7.3.2 Lookup Palette ......................................................................................................7-6
7.3.3 Temporal Modulated Energy Distribution (TMED) Dithering.................................7-6
7.3.4 Output FIFOs ........................................................................................................7-8
7.3.5 LCD Controller Pin Usage ....................................................................................7-8
7.3.6 DMA ......................................................................................................................7-9
7.4 LCD External Palette and Frame Buffers ........................................................................7-10
7.4.1 External Palette Buffer ........................................................................................7-10
7.4.2 External Frame Buffer.........................................................................................7-11
7.5 Functional Timing ............................................................................................................7-14
7.6 Register Descriptions.......................................................................................................7-17
7.6.1 LCD Controller Control Register 0 (LCCR0) .......................................................7-18
7.6.2 LCD Controller Control Register 1 (LCCR1) .......................................................7-24
7.6.3 LCD Controller Control Register 2 (LCCR2) .......................................................7-26
7.6.4 LCD Controller Control Register 3 (LCCR3) .......................................................7-28
7.6.5 LCD Controller DMA ...........................................................................................7-32
7.6.6 LCD DMA Frame Branch Registers (FBRx) .......................................................7-37
7.6.7 LCD Controller Status Register (LCSR)..............................................................7-38
7.6.8 LCD Controller Interrupt ID Register (LIIDR) ......................................................7-41
7.6.9 TMED RGB Seed Register (TRGBR) .................................................................7-42
7.6.10 TMED Control Register (TCR) ............................................................................7-43
7.7 LCD Controller Register Summary ..................................................................................7-44
8 Synchronous Serial Port Controller ..............................................................................................8-1
8.1 Overview............................................................................................................................8-1
8.2 Signal Description..............................................................................................................8-1
8.2.1 External Interface to Synchronous Serial Peripherals ..........................................8-1
8.3 Functional Description .......................................................................................................8-2
8.3.1 Data Transfer ........................................................................................................8-2
8.4 Data Formats .....................................................................................................................8-2
8.4.1 Serial Data Formats for Transfer to/from Peripherals ...........................................8-2
8.4.2 Parallel Data Formats for FIFO Storage ...............................................................8-6
8.5 FIFO Operation and Data Transfers ..................................................................................8-7
8.5.1 Using Programmed I/O Data Transfers ................................................................8-7
8.5.2 Using DMA Data Transfers ...................................................................................8-7
8.6 Baud-Rate Generation.......................................................................................................8-7
8.7 SSP Serial Port Registers..................................................................................................8-8
8.7.1 SSP Control Register 0 (SSCR0) .........................................................................8-8
8.7.2 SSP Control Register 1 (SSCR1) .......................................................................8-11
8.7.3 SSP Data Register (SSDR) ................................................................................8-15
8.7.4 SSP Status Register (SSSR) ..............................................................................8-16
8.8 SSP Controller Register Summary ..................................................................................8-19
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9 I C Bus Interface Unit ...................................................................................................................9-1
9.1 Overview............................................................................................................................9-1
9.2 Signal Description..............................................................................................................9-1
Intel® PXA255 Processor Developer's Manual
Contents
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