Psp Mode With Sscr1[Tte]=1 And Sscr1[Ttelp]=0 (Master To Frame); Psp Mode With Sscr1[Tte]=1 And Sscr1[Ttelp]=1 (Must Be Slave To Frame) - Intel PXA255 Developer's Manual

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Network SSP Serial Port

Figure 16-16. PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (master to frame)

(when SCMODE = 0)

(when SCMODE = 1)

(when SCMODE = 2)

(when SCMODE = 3)

(when SFRMP = 1)

(when SFRMP = 0)

SSCR1[TTELP] can only be set to 1 in PSP mode if the SSP is a slave to frame. If SSCR1[TTE] is

1 and SSCR1[TTELP] is 1 and the SSP is a slave to frame, SSPTXD is driven at the same clock

edge that the MSB is driven. SSPTXD is Hi-Z two clock edges after the clock edge that starts the

LSB. This occurs even if the SSP is a master of clock and this clock edge does not appear on the

SSPSCLK. If the SSP is a slave of clock, then the device driving SSPSCLK must provide another

Figure 16-17. PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=1 (must be slave to frame)

(when SCMODE = 0)

(when SCMODE = 1)

(when SCMODE = 2)

(when SCMODE = 3)

(when SFRMP = 1)

(when SFRMP = 0)

Figure 16-17

shows the pin timing for this mode.

Intel® PXA255 Processor Developer's Manual

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