Clocks Manager Block Diagram - Intel PXA255 Developer's Manual

The clocks manager also contains clock gating for power reduction.
Figure 3-1
The PXbus is the internal bus between the Core, the DMA/Bridge, the LCD Controller, and the
Memory Controller as shown in
optimal performance, the PXbus should be clocked as fast as possible. For example, if a target core
frequency of 200 MHz is desired use 200 MHz run mode instead of 200 MHz turbo mode with run
at 100 MHz. Increasing the PXbus frequency may help reduce the latency involved in accessing
non-cacheable memory.
Figure 3-1. Clocks Manager Block Diagram
Intel® PXA255 Processor Developer's Manual
shows a functional representation of the clocking network. "L" is in the core PLL.
Figure
32.768 k 32.768 k
RTC PWR_MGR
/1 /112
32.768
kHz
OSC
3.6864
MHz
OSC
RETAINS POWER IN SLEEP
USB FICP I2C
47.923 47.923 31.949
3-1. This bus is clocked at 1/2 the run mode frequency. For
3.6864 3.6864 3.6864
PWM SSP GPIO
100-400
MHz
PLL*
147.46
MHz
PLL
95.846
MHz
PLL
MMC UARTs
19.169 14.746
Clocks and Power Manager
3.6864
OST
CPU
CORE
/N
MEM
Controller
/M
/4 /2
DMA
LCD
/
Controller
Bridge
PXbus
AC97 I2S
12.288 5.672
3-3