Texas Instruments' Synchronous Serial Frame* Format - Intel PXA255 Developer's Manual

Synchronous Serial Port Controller
.
Figure 8-1. Texas Instruments' Synchronous Serial Frame* Format
SSPSCLK
SSPSFRM
SSPTXD
SSPRXD
SSPSCLK
SSPSFRM
SSPTX /RX Bit<0>
8.4.1.2 SPI Format Details
The SPI format has four sub-modes. The sub-mode used depends on the SSPSCLK edge selected
for driving and sampling data and on the phase mode of SSPSCLK selected (see
complete description of each mode).
In idle mode or when the SSP is disabled, SSPSCLK and SSPTXD are low and SSPSFRM is high.
When transmit (outgoing) data is ready, SSPSFRM goes low and stays low for the remainder of the
frame. The most significant serial data bit is driven onto SSPTXD a half-cycle later, and halfway
into the first bit period SSPSCLK asserts high and continues toggling for the remaining data bits.
Data transitions on the configured SSPSCLK edge. From 4 to 16 bits may be transferred per frame.
When SSPSFRM is asserted, receive data is simultaneously driven from the peripheral on
SSPRXD, most significant bit first. Data transitions on the configured SSPSCLK edge and is
sampled by the controller on opposite edge. At the end of the frame, SSPSFRM is deasserted high
one clock period after the last bit is latched at its destination and the completed incoming word is
shifted into the incoming FIFO. The peripheral can tristate SSPRXD after sending the last bit of the
frame. SSPTXD retains the last value transmitted when the controller goes into idle mode, unless
the SSP port is disabled or reset (which forces SSPTXD to zero).
For back-to-back transfers, start and completion are similar to those of a single transfer but
SSPSFRM does not deassert between words. Both transmitter and receiver know the word length
and internally keep track of the start and end of words (frames). There are no dead bits. One
frame's least significant bit is followed immediately by the next frame's most significant bit.
8-4
Bit<N-
Bit<N>
1>
Bit<N-
Bit<N>
1>
MSB 4 to 16 Bits
Single Transfer
...
...
Bit<N-
Bit<N> ... Bit<1>
1>
Continuous Transfers
...
...
... Bit<1> Bit<0>
... Bit<1> Bit<0>
LSB
Bit<N-
Bit<0> Bit<N>
1>
Intel® PXA255 Processor Developer's Manual
...
...
... Bit<1> Bit<0>
Section 8.7.2 for