Mmc_Cmdat Register (Mmc_Cmdat); Mmc_Cmdat Bit Definitions - Intel PXA255 Developer's Manual

MultiMediaCard Controller
Table 15-8. MMC_SPI Bit Definitions (Sheet 2 of 2)
Physical Address
0x4110_000c
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
Bits Name
0 SPI_EN
15.5.5

MMC_CMDAT Register (MMC_CMDAT)

MMC_CMDAT, shown in
starts the command sequence on the MMC bus when the MMC bus clock is turned on.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 15-9. MMC_CMDAT Bit Definitions (Sheet 1 of 2)
Physical Address
0x4110_0010
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
Bits Name
31:8
MMC_DMA_E
7
6
5 BUSY
15-26
MMC_SPI Register
reserved
0 0 0 0 0 0 0
SPI Mode Enable
0 – Disables SPI mode
1 – Enables SPI mode
Table 15-9, controls the command sequence. Writing to this register
MMC_CMDAT Register
reserved
0 0 0 0 0 0 0
— reserved
DMA Mode Enable
0 – Program I/O mode
1 – DMA mode
N
When DMA mode is used, this bit is a mask on RXFIFO_RD_REQ and TXFIFO_WR_REQ
interrupts.
80 Initialization Clocks
INIT
0 – Do not precede command sequence with 80 clocks
1 – Precede command sequence with 80 clocks
Specifies whether a busy signal is expected after the current command.
This bit is for no data command/response transactions only.
0 0 0 0 0 0 0 0
Description
0 0 0 0 0 0 0 0
Description
Intel® PXA255 Processor Developer's Manual
MultiMediaCard Controller
8 7 6 5 4 3
0 0 0 0 0 0 0 0
MultiMediaCard Controller
8 7 6 5 4 3
0 0 0 1 0 0 0 0
2 1 0
0 0 0
2 1 0
0 0 0