Mmc Controller Functional Description; Spi Mode Operation Without Data Token; Spi Mode Read Operation; Spi Mode Write Operation - Intel PXA255 Developer's Manual

MultiMediaCard Controller
Figure 15-4. SPI Mode Operation Without Data Token
from host to
card
MMCMD
MMDAT
Figure 15-5. SPI Mode Read Operation
from host to
MMCMD
MMDAT
Figure 15-6. SPI Mode Write Operation
from host to
MMCMD
MMDAT
Note: One- and three-byte data transfers are not supported with this controller. Data transfers of 10 or
more bytes are supported for stream writes only.
Refer to The MultiMediaCard System Specification for detailed information on MMC and SPI
modes of operation.
15.2

MMC Controller Functional Description

The software must read and write the MMC controller registers and FIFOs to initiate
communication to a card.
15-4
from card to
host
Command
Response
from card to
Command
Response
from card to
Command
Response
from host to
card
Command
data from card to
Data Block CRC
data from host to
Data response
Data Block
Data Response
Intel® PXA255 Processor Developer's Manual
from card to
host
Response Busy
Next
Command
new
Command
Busy