Ldcmdx Bit Definitions - Intel PXA255 Developer's Manual

LCD Controller
Table 7-10. LDCMDx Bit Definitions
Physical Address
channel 0: 0x4400_020C
channel 1: 0x4400_021C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reserved
Reset X X X X X 0
Bits Name
31:27
26
25:23
22 SOFINT
21 EOFINT
20:0
7-36
reserved
X X X 0 0 0 0
— reserved
Load Palette:
0 = DMA in progress is not the palette buffer.
PAL
1 = DMA in progress is the palette buffer.
PAL must not be set in LDCMD1.
— reserved
Start of Frame Interrupt:
0 = Do not set the SOF interrupt bit in the LCD status register when starting a new frame.
1 = Set the start of frame (SOF) interrupt bit in the LCD status register when starting a new
frame (after loading the frame descriptor).
End of Frame Interrupt:
0 = Do not set the EOF interrupt bit in the LCD status register when finished fetching the
last word of this frame.
1 = Set the end of frame (EOF) interrupt bit in the LCD status register when finished
fetching the last word of this frame.
Length of transfer in bytes:
The two lowest bits [1:0] are part of the length calculation but must always be zero for
LEN
proper memory alignment.
LEN = 0 is illegal.
LDCMD0
LDCMD1
0 0 0 0 0 0 0 0
Description
Intel® PXA255 Processor Developer's Manual
LCD Controller
8 7 6 5 4 3
LEN
0 0 0 0 0 0 0 0
2 1 0
0 0 0