I2C Status Register (Isr) - Intel PXA255 Developer's Manual

Table 9-10. ICR Bit Definitions (Sheet 3 of 3)
Physical Address
4030_1690
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
2 ACKNAK
1 STOP
0 START
2
9.9.4 I C Status Register (ISR)
The ISR, shown in
can use the ISR bits to check the status of the I
the ACK/NAK bit is completed on the I
The ISR also clears the following interrupts signalled from the I
•
IDBR Receive Full
•
IDBR Transmit Empty
•
Slave Address Detected
•
Bus Error Detected
•
STOP Condition Detect
•
Arbitration Lost
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Intel® PXA255 Processor Developer's Manual
2
I C Control Register
reserved
0 0 0 0 0 0 0 0
ACK/NAK Control: defines the type of ACK pulse sent by the I
receive mode.
2
0 = The I C unit sends an ACK pulse after it receives a data byte.
2
1 = The I C unit sends a negative ACK (NAK) after it receives a data byte.
2
The I C unit automatically sends an ACK pulse when it responds to its slave address or
when it responds in slave-receive mode, independent of the ACK/NAK control bit setting.
STOP: initiates a STOP condition after the next data byte on the I
master mode. In master-receive mode, the ACK/NAK control bit must be set along with this
bit. See Section 9.3.3.3
0 = Do not send a STOP.
1 = Send a STOP.
START: initiates a START condition to the I
Section 9.3.3.1 for more details on the START state.
0 = Do not send a START.
1 = Send a START.
Table 9-11, signals I
0 0 0 0 0 0 0 0
for more details on the STOP state.
2
C unit when in master mode. See
2
C interrupts to the processor interrupt controller. Software
2
C unit and bus. ISR bits (bits 9-5) are updated after
2
C bus.
2
2
I C Bus Interface Unit
2
I C Bus Interface Unit
8 7 6 5 4 3 2
0 0 0 0 0 0 0 0
2
C unit when in master-
2
C bus is transferred in
C unit:
1 0
0
9-25