I2C Control Register (Icr); Idbr Bit Definitions; Icr Bit Definitions - Intel PXA255 Developer's Manual

Intel computer hardware user manual
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on the acknowledge pulse in receiver mode. After the processor reads the IDBR, the ACK/NAK
Control bit is written and the Transfer Byte bit is written, allowing the next byte transfer to proceed
2
to the I
C bus. The IDBR register is 0x00 after reset.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 9-9. IDBR Bit Definitions
Physical Address
4030_1688
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset
0
0
0
0
0
0
31:8
7:0
2
9.9.3
I
C Control Register (ICR)
The processor uses the ICR, shown in
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 9-10. ICR Bit Definitions (Sheet 1 of 3)
Physical Address
4030_1690
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset
0
0
0
0
0
0
31:16
15
14
13
SADIE
12
ALDIE
11
SSDIE
Intel® PXA255 Processor Developer's Manual
2
I
C Data Buffer Register
reserved
0
0
0
0
0
0
0
reserved
2
IDB
I
C Data Buffer: Buffer for I
2
I
C Control Register
reserved
0
0
0
0
0
0
0
reserved
Fast Mode:
FM
0 = 100 KBit/sec. operation
1 = 400 KBit/sec. operation
Unit Reset:
UR
0 = No reset.
2
1 = Reset the I
C unit only.
Slave Address Detected Interrupt Enable:
0 = Disable interrupt.
2
1 = Enables the I
C unit to interrupt the processor when it detects a slave address match or
general call address.
Arbitration Loss Detected Interrupt Enable:
0 = Disable interrupt.
2
1 = Enables the I
C unit to interrupt the processor when it loses arbitration in master mode.
Slave STOP Detected Interrupt Enable:
0 = Disable interrupt.
2
1 = Enables the I
slave mode.
0
0
0
0
0
0
0
0
2
C bus send/receive data.
Table
9-10, to control the I
0
0
0
0
0
0
0
0
C unit to interrupt the processor when it detects a STOP condition in
2
I
C Bus Interface Unit
2
I
C Bus Interface Unit
8
7
6
5
4
3
IDB
0
0
0
0
0
0
0
0
2
C unit.
2
I
C Bus Interface Unit
8
7
6
5
4
3
0
0
0
0
0
0
0
0
2
1
0
0
0
0
2
1
0
0
0
9-23

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