Fdadrx Bit Definitions - Intel PXA255 Developer's Manual

word[1] contains the value for FSADRx
word[2] contains the value for FIDRx
word[3] contains the value for LDCMDx
Software must write the location of the first descriptor to FDADRx before enabling the LCD
controller. Once the controller is enabled, the first descriptor is read, and all four registers are
written by the DMAC. The next frame descriptor pointed to by FDADRx is loaded into the
registers for the associated DMA channel after all data for the current descriptor has been
transferred.
The address in FDADRx is not used when the BRA bit in the Frame Branch Register (FBRx) is set.
In this case, the Frame Branch Address is used to fetch the descriptor for the next frame. Branches
can be used to load a new palette or to process a regular frame, as detailed in
Note: If only one frame buffer is used in external memory, the FDADRx field (word[0] of the frame
descriptor) must point back to itself.
7.6.5.2 LCD DMA Frame Descriptor Address Registers (FDADRx)
FDADR0 and FDADR1, shown in
memory address of the next descriptor for the DMA channel. The DMAC fetches the descriptor at
this location after finishing the current descriptor. On reset, the bits in this register are undefined.
The target address must be aligned to a 16-byte boundary. Bits [2:0] of the address must be zero.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 7-7. FDADRx Bit Definitions
Physical Address
channel 0: 0x4400_0200
channel 1: 0x4400_0210
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset ? ? ? ? ? ?
Bits Name
Descriptor
31:0
Address
7.6.5.3 LCD DMA Frame Source Address Registers (FSADRx)
FSADR0 and FSADR1, shown in
source address of the current descriptor for the DMA channel. The address must be aligned on an
8-byte boundary. Bits [2:0] must be zero. If this descriptor is a palette load, FSADRx points to the
memory location at the beginning of the palette data. The size of the palette data must be four 16-
bit entries for 1- and 2-bit pixels, sixteen 16-bit entries for 4-bit pixels, or 256 16-bit entries for 8-
bit pixels. If this descriptor is for pixel data, FSADRx points to the beginning of the frame buffer in
memory. This address is incremented as the DMAC fetches from memory. If desired, the DMA
Frame ID Register can be used to hold the initial frame source address.
These read-only registers are loaded indirectly via the frame descriptors, as described in
Section 7.6.5.1.
Intel® PXA255 Processor Developer's Manual
Table
FDADR0
FDADR1
Descriptor Address
? ? ? ? ? ? ? ?
Address of next descriptor.
Bits [2:0] must be zero for proper memory alignment.
Table
7-7, correspond to DMA channels 0 and 1 and contain the
? ? ? ? ? ? ? ?
Description
7-8, correspond to DMA channels 0 and 1 and contain the
LCD Controller
Section 7.6.6.
LCD Controller
8 7 6 5 4 3 2
? ? ? ? ? ? ? ?
1 0
? ?
7-33