Msb-Justified Data Formats (16 Bits - Intel PXA255 Developer's Manual

Figure 14-1
modes of operations.
Data is transmitted and received in frames of 64 BITCLK cycles. Each frame consists of a Left
sample and a Right sample. Each frame holds 16-bits of valid sample data (shown in the figures)
and 16-bits of padded zeros (not shown in the figures). The transmit and receive FIFOs only hold
valid sample data (not padded zero data).
In the Normal I
the MSB of each data sample lags behind the SYNC edges by one BITCLK cycle.
In the MSB-Justified mode, the SYNC is high for the Left sample and low for the Right sample.
Also, the MSB of each data sample is aligned with the SYNC edges.
2
Figure 14-1. I S Data Formats (16 bits)
BITCLK
SData_Out
Note: Timing for SData_In is identical to SData_Out.
Figure 14-2. MSB-Justified Data Formats (16 bits
BITCLK
SData_Out
Note: Timing for SData_In is identical to SData_Out.
Intel® PXA255 Processor Developer's Manual
and Figure 14-2 provide timing diagrams that show formats for I
2
S mode, the SYNC is low for the Left sample and high for the Right sample. Also,
cycle0
0 1 2 3 13 14 15 16
15 14 13 3 2
SYNC
cycle0
0 1 2 3 13 14 15 16
15 14 13 3 2 1
SYNC
Inter-Integrated-Circuit Sound (I2S) Controller
29 30 31 32 33 34 35
1 0 15 14 13 12 3
Left
29 30 31 32 33 34 35
0 15 14 13 12 3
Left
2
S and MSB-justified
45 46 47 48 62 63 0
2 1 0
Right
A8842-01
45 46 47 48 62 63 0
2 1 0
Right
A8843-01
14-7