Output Fifos; Lcd Controller Pin Usage; Tmed Block Diagram - Intel PXA255 Developer's Manual

LCD Controller
Figure 7-4. TMED Block Diagram
frame_clk
TCR<1>
TCR<3>
TSR<7:0>
TCR<2>
TCR<0>
TCR<13:12>
pixel
data
Single Color Component Path (RED)
Single Color Component Path (GREEN)
Single Color Component Path (BLUE)
TCR<7:4>
pixel clk
line clk
TCR<11:8>
TCR<14>
7.3.4

Output FIFOs

The LCD controller has two output FIFOs to queue pixel data before it is sent out to the pins. Each
output FIFO is 16 bytes, organized as 16 entries by 8 bits wide. Pixel values are accumulated in a
serial shifter and written to the FIFO buffers in 4-, 8-, or 16-bit quantities. Four pins are used for
single-panel monochrome screens, 8 pins are used for single- and dual-panel monochrome screens
and single-panel color displays, and 16 pins are used for dual-panel color and active displays. Each
time a value is taken from the bottom of the FIFO, the entry is invalidated, and all data in the FIFO
moves down one position.
7.3.5

LCD Controller Pin Usage

The timing of the line (L_LCLK) and frame (L_FCLK) clocks is programmable to support both
passive display and active display modes. Programming options include: wait state insertion at the
beginning and end of each line and frame, pixel clock (L_PCLK), line clock, frame clock
(L_FCLK), output enable signal polarity, and frame clock pulse width.
See Section 7.5
used for GPIO. See
7-8
Frame
Frame
Counter
Number
Adjuster
Color
Offset
Adjuster
Color Value
Generator
force to 1
Pixel Number
Line Counter
Adjustor
Pixel Counter
for pin timing diagrams. When the LCD controller is disabled, all of its pins can be
Chapter 4, "System Integration Unit"
TCR is the TMED Control Register
TSR is the TMED Seed Register
FN
Lower Boundary
Generator
LB =FN x CV + Offset
LB
Upper Boundary
CV
Generator
UB =LB + CV
Address
Generator
for further details. See also
Intel® PXA255 Processor Developer's Manual
LB
Data
UB Outpu
Generator
Data
LB > ME > UB
Bit
or Pixel > 253
Outpu
Data
Bit
Outpu
Data
Bit
ME
Matrix
Table 7-1.