Intel PXA255 Developer's Manual page 56

System Architecture
Table 2-8. System Architecture Register Address Summary (Sheet 6 of 12)
Unit Address
0x4050_0114
0x4050_0118
0x4050_011C
through
0x4050_013C
0x4050_0140
0x4050_0144
through
0x4050_01FC
0x4050_0200
through
0x4050_02FC
0x4050_0300
through
0x4050_03FC
0x4050_0400
through
0x4050_04FC
0x4050_0500
through
0x4050_05FC
UDC 0x4060_0000
0x4060_0000
0x4060_0008
0x4060_0010
0x4060_0014
0x4060_0018
0x4060_001C
0x4060_0020
0x4060_0024
0x4060_0028
0x4060_002C
0x4060_0030
0x4060_0034
0x4060_0038
0x4060_003C
0x4060_0040
0x4060_0044
0x4060_0048
0x4060_004C
0x4060_0060
0x4060_0064
2-26
Register Symbol
— Reserved
MISR Modem In Status Register
— Reserved
MODR Modem FIFO Data Register
— Reserved
— Primary Audio CODEC registers
— Secondary Audio CODEC registers
— Primary Modem CODEC registers
— Secondary Modem CODEC registers
UDCCR UDC Control Register
UDCCFR UDC Control Function Register
UDCCS0 UDC Endpoint 0 Control/Status Register
UDCCS1 UDC Endpoint 1 (IN) Control/Status Register
UDCCS2 UDC Endpoint 2 (OUT) Control/Status Register
UDCCS3 UDC Endpoint 3 (IN) Control/Status Register
UDCCS4 UDC Endpoint 4 (OUT) Control/Status Register
UDCCS5 UDC Endpoint 5 (Interrupt) Control/Status Register
UDCCS6 UDC Endpoint 6 (IN) Control/Status Register
UDCCS7 UDC Endpoint 7 (OUT) Control/Status Register
UDCCS8 UDC Endpoint 8 (IN) Control/Status Register
UDCCS9 UDC Endpoint 9 (OUT) Control/Status Register
UDCCS10 UDC Endpoint 10 (Interrupt) Control/Status Register
UDCCS11 UDC Endpoint 11 (IN) Control/Status Register
UDCCS12 UDC Endpoint 12 (OUT) Control/Status Register
UDCCS13 UDC Endpoint 13 (IN) Control/Status Register
UDCCS14 UDC Endpoint 14 (OUT) Control/Status Register
UDCCS15 UDC Endpoint 15 (Interrupt) Control/Status Register
UFNRH UDC Frame Number Register High
UFNRL UDC Frame Number Register Low
Register Description
Intel® PXA255 Processor Developer's Manual