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R
5.3.2.2.
V
CC-CORE
There is only one enable pin, VR_ON, used to enable the outputs of the voltage regulator. When
VR_ON is low, all output voltage rails (V
VR_ON is high, V
illustrates the power on sequencing timing.
Figure 48. Power On Sequencing Timing Diagram
NOTES:
Desired, but not required feature of a processor and chipset regulator controller. If not implemented by the
1.
controller, both the CLK_ENABLE# and the t
Figure 48 depicts a number of signals that may or may not be platform visible.
2.
See Section 11.4 for platform power sequencing details and timing requirements.
5.4.
V
Output Requirements
CCP
The V
output voltage rail provides power to the FSB rail for the Intel Pentium M/Intel Celeron M
CCP
processor, the Intel 855PM MCH, the 82801DBM ICH4-M, and ITP700FLEX debug port if it is used.
For the ICH4-M, this rail is known as V
®
Intel
855PM Chipset Platform Design Guide
Power Sequencing
, V
and V
CCP
CC_MCH
CC-CORE
VID
t
SFT_START_VCC
-12%
VR_ON
V
CC-CORE
CPU_UP
V
CCP
Vccp_UP
V
CC_MCH
MCH_PWRGD
CLK_ENABLE#
See Note 1.
IMVP4_PWRGD
, V
and V
CC-CORE
CCP,
CC_MCH
are commanded ramp up at the same time. Figure 48
t
BOOT
t
BOOT-VID-TR
t
CPU_UP
-12%
t
Vccp_UP
- 12%
t
MCH-PWRGD
t
CPU_PWRGD
See Note 1.
timer must be implemented by platform control logic.
CPU-PWRGD
The voltage regulator can be programmed via an external
CPU_IO.
Platform Power Requirements
) are driven to a 0-V state. When
V
V
BOOT
VID
97
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