Case 9: Ep5 Data Transmit (Interrupt-In); Case 10: Reset Interrupt - Intel PXA255 Developer's Manual

USB Device Controller
6. Return from interrupt.
7. Steps
12.5.8.3 Software Enables the SOF Interrupt
If software enables the SOF interrupt to handle the transaction on a frame count basis:
1. Software disables the UDCCS4 Interrupt by setting UICR0[IM4] to a 1 and enables the SOF
interrupt in the UFNHR register by setting UFNHR[SIM] to a 0.
2. When the host PC sends an SOF, the UDC sets the UFNHR[SIR] bit, which causes an SOF
interrupt.
3. If UDCCS4[RNE] is clear and UDCCS4[RSP] is clear, no data packet was received.
4. If UDCCS4[RNE] is clear and UDCCS4[RSP] is set, the data packet was a zero-length packet.
5. If UDCCS4[RNE] is set, the data packet was a short packet and software uses the UDCWC4
count register to read the proper amount of data from the EP4 data FIFO (UDDR4).
6. Software clears the UDCCS4[RPC] and UFNHR[SIR] bits.
7. Return from interrupt.
8. Steps
12.5.9

Case 9: EP5 Data Transmit (INTERRUPT-IN)

The procedure in Case 9 can also be used to operate Endpoints 10 and 15.
In Case 9, the Transmit Short Packet is only set if a packet size of less than 8 bytes is sent. If the
packet size is 8 bytes, the system arms when the 8th byte is loaded. Loading the 8th byte and
setting the UDCCS5[TSP] bit produces one 8-byte packet and one zero-length packet.
When software receives a SETUP VENDOR command to set up an EP5 INTERRUPT-IN
transaction, it can only allow the Megacell to handle the transaction:
1. During the SETUP VENDOR command, software fills the EP5 data FIFO (UDDR5) with data
and clears the UDCCS5[TPC] bit.
2. The host PC sends an INTERRUPT-IN and the UDC generates an EP5 Interrupt.
3. Software fills the EP5 data FIFO (UDDR5) with data and clears the UDCCS5[TPC] bit. If the
data packet is a short packet, software also sets the UDCCS5[TSP] bit.
4. Return from interrupt.
5. Steps
12.5.10

Case 10: RESET Interrupt

1. After a system reset, software loads the registers with the required values.
2. Software enables the UDC by setting the UDCCR[UDE] bit and immediately reads the
UDCCR[UDA] bit to determine if a USB reset is currently on the USB bus.
a. If UDCCR[UDA] is a 0, there is currently a USB reset on the bus and software clears the
interrupt by writing a 1 to the UDCCR[RSTIR] bit. Software enables future reset
interrupts by clearing the UDCCR[REM] bit.
12-20
2 through 6 repeat until all the data has been read from the host.
2 through 7 repeat until all the data is sent to the host PC.
2 through 4 repeat until all the data is sent to the host PC.
Intel® PXA255 Processor Developer's Manual