Picr Bit Definitions - Intel PXA255 Developer's Manual

AC'97 Controller Unit
Table 13-9. POCR Bit Definitions (Sheet 2 of 2)
Physical Address
4050_0000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
Bits Name
3 FEIE
2:0
13.8.3.4 PCM-In Control Register (PICR)
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 13-10. PICR Bit Definitions
Physical Address
4050_0004
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
Bits Name
31:4
3 FEIE
2:0
13-24
POCR Register
reserved
0 0 0 0 0 0 0
FIFO Error Interrupt Enable (FEIE)
This bit controls whether the occurrence of a transmit FIFO error will cause an interrupt or
not.
0 = No interrupt will occur even if bit 4 in the POSR is set
1 = An interrupt will occur if bit 4 in the POSR is set.
— reserved
PICR Register
reserved
0 0 0 0 0 0 0
— reserved
FIFO Error Interrupt Enable (FEIE)
This bit controls whether the occurrence of a receive FIFO error will cause an interrupt or
not.
0 = No interrupt will occur even if bit 4 in the PISR is set
1 = An interrupt will occur if bit 4 in the PISR is set.
— reserved
0 0 0 0 0 0 0 0
Description
0 0 0 0 0 0 0 0
Description
Intel® PXA255 Processor Developer's Manual
AC'97 Controller Unit
8 7 6 5 4 3
0 0 0 0 0 0 0 0
AC'97 Controller Unit
8 7 6 5 4 3
0 0 0 0 0 0 0 0
2 1 0
0 0 0
2 1 0
0 0 0