Uicr0 Bit Definitions - Intel PXA255 Developer's Manual

Table 12-20. UICR0 Bit Definitions
0x 4060_0050
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset x x x x x x
Bits Name
31:8
7
6
5
4
3
2
1
0
12.6.9.1 Interrupt Mask Endpoint x (IMx), Where x is 0 through 7
The UICR0[IMx] bit is used to mask or enable the corresponding endpoint interrupt request,
USIR0[IRx]. When the mask bit is set, the interrupt is masked and the corresponding bit in the
USIR0 register is not allowed to be set. When the mask bit is cleared and an interruptible condition
occurs in the endpoint, the appropriate interrupt bit is set. Programming the mask bit to a 1 does not
affect the current state of the interrupt bit. It only blocks future zero to one transitions of the
interrupt bit.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Intel® PXA255 Processor Developer's Manual
reserved
x x x x x x x
— reserved
Interrupt Mask for Endpoint 7
IM7
0 = Receive interrupt enabled
1 = Receive interrupt disabled
Interrupt Mask for Endpoint 6
IM6
0 = Transmit interrupt enabled
1 = Transmit interrupt disabled
Interrupt mask for Endpoint 5
IM5
0 = Transmit interrupt enabled
1 = Transmit interrupt disabled
Interrupt mask for Endpoint 4
IM4
0 = Receive Interrupt enabled
1 = Receive Interrupt disabled
Interrupt mask for Endpoint 3
IM3
0 = Transmit interrupt enabled
1 = Transmit interrupt disabled
Interrupt Mask for Endpoint 2
IM2
0 = Receive interrupt enabled
1 = Receive interrupt disabled
Interrupt Mask for Endpoint 1
IM1
0 = Transmit interrupt enabled
1 = Transmit interrupt disabled
Interrupt mask for endpoint 0
IM0
0 = Endpoint zero interrupt enabled
1 = Endpoint zero interrupt disabled
UICR0
x x x x x x x x
Description
USB Device Controller
USB Device Controller
8 7 6 5 4 3
x x x 1 1 1 1 1
2 1 0
1 1 1
12-37