Autoflow Control; Auto-Baud-Rate Detection - Intel PXA255 Developer's Manual

Note: Ensure that the DMA controller has completed the previous receive DMA requests before the error
interrupt handler begins to clear the errors from the FIFO. If not, FIFO underflow could occur.
17.4.2.6 Removing Trailing Bytes In DMA Mode
When the number of entries in the receive FIFO is less than its trigger threshold, and no additional
data is received, the remaining bytes are called trailing bytes. The remaining bytes must then be
removed via the processor as described in
17.4.3

Autoflow Control

Autoflow control uses the clear to send (nCTS) and request to send (nRTS) signals to automatically
control the flow of data between the UART and external modem. When autoflow is enabled, the
remote device is not allowed to send data unless the UART asserts nRTS low. If the UART
deasserts nRTS while the remote device is sending data, the remote device is allowed to send one
additional byte after nRTS is deasserted. An overflow could occur if the remote device violates this
rule. Likewise, the UART is not allowed to transmit data unless the remote device asserts nCTS
low. This feature increases system efficiency and eliminates the possibility of a receive FIFO
overflow error due to long interrupt latency.
Autoflow mode can be used in two ways: full autoflow, automating both nCTS and nRTS; and half
autoflow, automating only nCTS. Full autoflow is enabled by setting MCR[AFE] and MCR[RTS]
to 1. Auto-nCTS-only mode is enabled by setting MCR[AFE] and clearing MCR[RTS].
When in full autoflow mode, nRTS is asserted when the UART FIFO is ready to receive data from
the remote transmitter. This occurs when the amount of data in the receive FIFO is below the
programmable trigger threshold value. When the amount of data in the receive FIFO reaches the
programmable trigger threshold, nRTS is deasserted. It is asserted once again when enough bytes
are removed from the FIFO to lower the data level below the trigger threshold.
When in full or half-autoflow mode, nCTS is asserted by the remote receiver when the receiver is
ready to receive data from the UART. The UART checks nCTS before sending the next byte of data
and will not transmit the byte until nCTS is low. If nCTS goes high while the transfer of a byte is in
progress, the transmitter sends the byte.
Note: Autoflow mode can be used only in conjunction with FIFO mode.
17.4.4

Auto-Baud-Rate Detection

The HWUART supports auto-baud-rate detection. When enabled, the UART counts the number of
14.7456 MHz clock cycles within the start-bit pulse. This number is then written into the Auto-
Baud-Count register (ACR, see
is written, a auto-baud-lock interrupt is generated (if enabled), and the UART automatically
programs the Divisor Latch registers
the processor can read the ACR and use this information to program the Divisor-Latch registers
with a baud rate calculated by the processor. After the baud rate has been programmed, it is the
responsibility of the processor to verify that the predetermined characters (usually AT or at) are
being received correctly. For the autobaud rate detection circuit to work correctly, the first data bit
transmitted after the start bit must be a logic '1'. If a logic '0' is transmitted, the auto-baud circuit
counts the zero as part of the start bit, resulting in an incorrect baud rate being programmed into the
Divisor Latch Register Low (DLL) and Divisor Latch Register High (DLH) registers.
Intel® PXA255 Processor Developer's Manual
Section 17.4.2.1.
Table 17-13) and is used to calculate the baud rate. When the ACR
(Section 17.5.3) with the appropriate baud rate. If preferred,
Hardware UART
17-7