Synchronous Static Memory Timing Diagrams; Sxmrs Bit Definitions - Intel PXA255 Developer's Manual

Memory Controller
SXCNFG[RL] fields must match any CAS latencies and RAS latencies programmed in this
SXMRS register. Software must ensure that fields match the latencies. In some cases, duplicate
information must be programmed.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 6-16. SXMRS Bit Definitions
0x4800_0024
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
Bits Name
31
30:16 SXMRS2
15
14:0 SXMRS0
6.6.3

Synchronous Static Memory Timing Diagrams

Figure 6-12
6-38
SXMRS2
1 0 0 0 1 1 0
— reserved
MRS value to be written to Synchronous Static memory requiring an MRS command for
Bank Pair 2
— reserved
MRS value to be written to Synchronous Static Memory requiring an MRS command for
Bank Pair 0
shows a three-beat read cycle for SMROM.
SXMRS
0 1 0 0 0 0 0 0
Description
Intel® PXA255 Processor Developer's Manual
Memory Controller
8 7 6 5 4 3
SXMRS0
0 1 0 0 0 1 1 0
2 1 0
0 1 0