Page 1 ® Intel PXA27x Processor Family Design Guide May 2005 Order No. 280001-002...
Page 2 Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.
Page 3: Table Of Contents
Document Organization and Overview ................I: 1-1 Functional Overview .......................I: 1-2 Package Introduction ......................I: 1-3 Signal Pin Descriptions ....................I: 1-4 PCB Design Guidelines......................I: 2-1 ® Intel Flash Memory Design Guidelines .................I: 2-1 General PCB Characteristics ..................I: 2-1 2.2.1 PCB Layer Assignment (Stackup) ..............I: 2-2 2.2.2 PCB Component Placement ................I: 2-4...
Page 4 Block Diagram...................II: 5-4 5.5.1.3 Layout Notes..................II: 5-4 5.5.2 Flow-Through DMA Transfers ................II: 5-5 5.5.2.1 Signals ....................II: 5-5 5.5.2.2 Block Diagram...................II: 5-5 5.5.2.3 Layout Notes..................II: 5-6 System Memory Interface ......................II: 6-1 Overview........................II: 6-1 Signals ...........................II: 6-3 ® Intel PXA27x Processor Family Design Guide...
Page 5 Modes of Operation Overview ..................II: 7-6 7.5.1 Passive Monochrome Single-Scan Mode ............II: 7-6 7.5.1.1 Signals ....................II: 7-6 7.5.1.2 Schematics/Block Diagram ...............II: 7-7 7.5.1.3 Layout Notes..................II: 7-7 7.5.2 Passive Monochrome Single-Scan Double-Pixel Mode........II: 7-8 ® Intel PXA27x Processor Family Design Guide...
Page 6 Inter-Integrated Circuit (I2C)....................II: 9-1 Overview........................II: 9-1 Signals ...........................II: 9-1 Schematic/Block Diagram....................II: 9-2 9.3.1 Digital-to-Analog Converter (DAC) ..............II: 9-2 9.3.2 Other Uses of I2C .....................II: 9-3 9.3.3 Pull-Ups and Pull-Downs ..................II: 9-4 Layout Notes........................II: 9-4 ® Intel PXA27x Processor Family Design Guide...
Page 7 Modes of Operation Overview ..................II: 14-4 14.5.1 PXA27x Processor Provides BITCLK signal to CODEC.........II: 14-4 14.5.1.1 Signals ....................II: 14-4 14.5.1.2 Block Diagram.................II: 14-5 14.5.2 CODEC Provides BITCLK Signal to PXA27x Processor ........II: 14-6 ® Intel PXA27x Processor Family Design Guide...
Page 8 18.5.2 Keypad Matrix and Direct Keys with One Rotary Encoder ......II: 18-8 18.5.2.1 Signals ....................II: 18-8 18.5.2.2 Block Diagram.................II: 18-9 18.5.3 Keypad Matrix and Direct Keys with Two Rotary Encoders ......II: 18-10 18.5.3.1 Signals ..................II: 18-10 18.5.3.2 Block Diagram................II: 18-11 ® viii Intel PXA27x Processor Family Design Guide...
Page 9 Overview ........................II: 24-1 24.2 Signals .........................II: 24-1 24.3 Block Diagram/Schematic....................II: 24-3 24.4 Layout Notes........................II: 24-3 Interrupt Interface.........................II: 25-1 25.1 Overview ........................II: 25-1 25.2 Signals .........................II: 25-2 25.3 Block Diagram ......................II: 25-3 25.4 Layout Notes........................II: 25-4 ® Intel PXA27x Processor Family Design Guide...
Page 10 26.4.4.1 Bypass Register................II: 26-7 26.4.4.2 Boundary-Scan Register..............II: 26-8 26.4.4.3 Data-Specific Registers ..............II: 26-9 26.4.4.4 Flash Data Register ................II: 26-9 ® 26.4.4.5 Intel XScale Data Registers............II: 26-9 26.4.5 Test Access Port (TAP) Controller..............II: 26-10 26.4.5.1 Test-Logic-Reset State ..............II: 26-11 26.4.5.2 Run-Test/Idle State ...............II: 26-11 26.4.5.3 Select-DR-Scan State..............II: 26-11...
Page 11 PXA27x Processor Developer’s Kit (DVK) ................II: B-1 PXA27x DVK Bill-of-Materials....................II: C-1 ® ® Intel PXA27x Processor and Intel PXA25x Processor Differences....... II: D-1 Companion Components for PXA27x Processor ............... II: E-1 Glossary ........................Glossary-1 Index ............................IX-1 ®...
Page 12 7-6 Active Color 12-bit per pixel Display Typical Connection ............II: 7-16 7-7 Active Color 16-bit-per-pixel Display Typical Connection ............II: 7-18 7-8 Active Color 18-bit-per pixel Display Typical Connection ............II: 7-20 7-9 Active Color Display 24-bit Typical Connection ..............II: 7-22 ® Intel PXA27x Processor Family Design Guide...
Page 13 26-1 Test Access Port (TAP) Block Diagram................II: 26-2 26-2 PXA27x Scan Chain Arrangement ..................II: 26-5 26-3 TAP Controller State Diagram ...................II: 26-10 27-1 Block Diagram for 8-bit Master Parallel Interface ..............II: 27-3 27-2 Interface Options Summary ....................II: 27-4 ® Intel PXA27x Processor Family Design Guide xiii...
Page 14 A-3 Daughter Card Block Diagram....................II: A-4 A-4 Liquid Crystal Display Block Diagram................... II: A-5 A-5 Audio Module Block Diagram ....................II: A-6 A-6 Keyboard Block Diagram...................... II: A-7 A-7 JTAG Block Diagram ......................II: A-8 ® Intel PXA27x Processor Family Design Guide...
Page 15 7-10 LCD Interface Signal List .....................II: 7-19 7-11 Active Display Pins Required....................II: 7-21 8-1 SSP Serial Port I/O Signals ....................II: 8-2 9-1 I2C Signal Description ......................II: 9-1 10-1 UART Signal Descriptions ....................II: 10-2 10-2 FFUART Interface Signals....................II: 10-3 ® Intel PXA27x Processor Family Design Guide...
Page 16 B-3 Processor Developer’s Kit ....................II: B-2 D-1 PXA27x Processor Operating Modes not Supported by the PXA25x Processor ....II: D-2 E-1 Crystal Devices........................II: E-1 E-2 Manufacturers of PMIC Devices................... II: E-2 E-3 USB OTG Transceivers......................II: E-4 ® Intel PXA27x Processor Family Design Guide...
Page 17 Section 6.5.5, “Variable Latency Input/Output (VLIO) Interface,” on May, 2005 page II: 6-21 Updated Connection to OTG ID, Figure 12-7, “Connection to External OTG Charge Pump” on page II:12-10. April 2004 Initial release §§ ® Intel PXA27x Processor Family Design Guide xvii...
Page 18 Contents ® xviii Intel PXA27x Processor Family Design Guide...
Page 19: Introduction To Part I
• Intel PXA270 Processor – discrete processor ® • Intel PXA271 Processor – 32 Mbytes of Intel StrataFlash® Memory and 32 Mbytes of Low Power SDRAM ® • Intel PXA272 Processor – 64 Mbytes of Intel StrataFlash® Memory The schematics in Appendix B , “PXA27x Processor Developer’s Kit (DVK)”...
Page 20: Functional Overview
Flash Memory Design for a Stacked Chip Scale Package (SCSP) Application Note 252802-002 Functional Overview ® The PXA27x processor offers an integrated system-on-a-chip design based on the Intel XScale ® Microarchitecture. The PXA27x processor integrates the Intel XScale Microarchitecture core with many on-chip peripherals that allows design of many different products for the handheld and cellular handset markets.
Page 21: Package Introduction
0.50 mm (0.0197 inches) VF-BGA molded matrix array package with 32-bit functionality. The ® ® Intel PXA271 Processor and Intel PXA272 Processor are available in a 14 mm x 14 mm (0.551 x 0.551 inches), 336-pin 0.65 mm (0.0256 inches) FS-CSP with 32-bit functionality. Refer to Part I Section 1.3, “Package Introduction,”...
Page 22: Signal Pin Descriptions
Signal Pin Descriptions ® Refer to Chapter 2, “System Architecture” of the Intel PXA27x Processor Family Developers Manual for description of the signal descriptions for the PXA27x processor. Refer to this section for information regarding specific pin assignments and allocation.
Page 23: Pcb Design Guidelines
PCB Design Guidelines ® This chapter provides printed-circuit board (PCB) design guidelines for the Intel PXA27x Processor Family (PXA27x processor). The PXA27x processor family dimensions and package types are: • PXA270 processor – 13 mm x 13 mm (0.512 x 0.512 inches) high density chip scale package (VF-BGA) package.
Page 24: Pcb Layer Assignment (Stackup)
Follow the recommendations for surface finish and requirements for physical testing: • Surface Finish OSP — Use Organic Solder Preservatives (OSP) Entek 106A. — Ensure that land pads are as flat as possible (no HASL). ® I:2-2 Intel PXA27x Processor Family Design Guide...
Page 25: Recommended Pcb Layer Assignment For An Eight-Layer Pcb
— Moving point probe damages pads that affect mechanical testing results. Therefore, do not perform physical tests of PCBs. Figure 2-2. Recommended PCB Layer Assignment for an Eight-Layer PCB SIGNAL-1 SIGNAL-2 GROUND-1 VCC-IO (DIVIDED) VCC_CORE SIGNAL-3 GROUND-2 SIGNAL-4 ® Intel PXA27x Processor Family Design Guide I:2-3...
Page 26: Pcb Component Placement
In general, reserve the space on the bottom layer of the PCB under the package for the high- frequency decoupling caps and clock crystals. Install the high-frequency caps and clock crystals on the bottom layer before installing bulk decoupling caps or other components. ® I:2-4 Intel PXA27x Processor Family Design Guide...
Page 27 Figure 2-4. VF-BGA 13mm x 13mm Component Layout Placement Guide (Top View) MEMORY I/O USIM MEMORY I/O CLOCK & POWER CONTROL MEMORY I/O BASEBAND I/F PERIPHERAL I/O VCC BALL CORE BATT USIM SRAM VSS BALL ® Intel PXA27x Processor Family Design Guide I:2-5...
Page 28 PCB Design Guidelines Figure 2-5. FS-CSP 14mm x 14mm Component Layout Placement Guide (Top View) CLOCK & POWER CONTROL USIM MEMORY VCC BALL CORE BATT USIM SRAM VSS BALL ® I:2-6 Intel PXA27x Processor Family Design Guide...
Page 29: Pcb Escape Routing
PCB fabrication technology or micro-vias to route signals from the inner rows of balls on these packages: • 0.5 mm (0.0197 inches) ball pitch packages (for example, VF-BGA) • 0.65 mm (0.0256 inches) ball pitch packages (for example, FS-CSP) ® Intel PXA27x Processor Family Design Guide I:2-7...
Page 30: Vf-Bga Escape Routing
E: Typical Micro Via (Via-in-Pad) Size E: Typical Micro Via (Via-in-Pad) Size Top View Top View Land Pad Land Pad Land Pad Solder Mask Solder Mask Solder Mask Side View Side View ® I:2-8 Intel PXA27x Processor Family Design Guide...
Page 31: Fs-Csp Escape Routing
F: Spaces (2 traces) G: Max Via Capture Pad H: Max Via Drill Size I: Typical Micro Via (Via-in-Pad) Drill Size Land Pad Land Pad Top View Solder Mask Solder Mask Side View ® Intel PXA27x Processor Family Design Guide I:2-9...
Page 32: Pbga Escape Routing
D: Reduced Trace Width Between Land Pads 0.0889 (0.0035) E: Trace Width (2 Traces) 0.090 (0.0035) F: Spaces (2 Traces) 0.090 (0.0035) G: Typical Micro Via (Via-in-Pad) Drill Size Notes: 1. All dimensions are in mm (inches). ® I:2-10 Intel PXA27x Processor Family Design Guide...
Page 33: Pcb Keep-Out Zones
14.5 mm (package edge is always 2.5mm from support point). Figure 2-9 for illustration of the PCB recommended dimensions. Figure 2-9. Recommended Mobile Handset Dimensions Diagram ® Intel PXA27x Processor Family Design Guide I:2-11...
Page 34: Power Supply Decoupling Requirements
Silicon Daisy Chain (SDC) Evaluation Units Intel also offers evaluation units that have been internally shorted together (to the silicon) in a daisy chain pattern. This ensures that the I/O path of the package is complete through the ball, substrate, lead beam or bond wire, silicon, and back down through a separate I/O path.
Page 35: Preconditioning And Moisture Sensitivity
Preconditioning and Moisture Sensitivity With most surface mount components, if the units are allowed to absorb moisture beyond a certain ® point, package damage occurs during the reflow process. Refer to Chapter 8 in the Intel Packaging Data Book at http://www.intel.com/design/PACKTECH/packbook.htm for package preconditioning and moisture sensitivity requirements.
Page 36 PCB Design Guidelines Figure 2-11. PBGA (23x23) Tray Specification §§ ® I:2-14 Intel PXA27x Processor Family Design Guide...
Page 37: Design Check List
Design Check List ® For design check list information, refer to the Intel PXA27x Processor Family Design Check List Application Note. See Table 1-1 for ordering information. §§ Intel® PXA27x Processor Family Design Guide I:3-1...
Page 38 Design Check List I:3-2 Intel® PXA27x Processor Family Design Guide...
Page 39: Mixed Voltage Design Considerations
Mixed Voltage Design Considerations Overview ® The Intel PXA27x Processor Family (PXA27x processor) uses a complex power management system that provides the best possible power utilization. The power management system requires design of several voltage supplies into your system. Use a sophisticated power management integrated circuit (PMIC) in your system in order to utilize all the power savings possible with the PXA27x processor.
Page 40: Example Power Supply Utilizing Minimal Regulators
The 1.8 V regulators are shown in dashed lines to indicate where the regulators are used. Use either the dashed black lines or the dashed lines if that peripheral is used in the system. However, ensure both voltages (if used) are not connected together. ® I:4-2 Intel PXA27x Processor Family Design Guide...
Page 41 BATT_FAULT Reference voltage* VCC_FAULT High Reference voltage** * Battery level where system must enter deep sleep until main battery is recharged. ** Battery level where system should save state and enter sleep. ® Intel PXA27x Processor Family Design Guide I:4-3...
Page 42: Cautions
To avoid drainage of backup battery and to allow the backup battery to remain connected after production, boot the device and then place the device in deep sleep mode. §§ ® I:4-4 Intel PXA27x Processor Family Design Guide...
Page 43: Power Measurements
Power Measurements Overview ® The Intel PXA27x Processor Family (PXA27x processor) employs a complex power management system that provides the best possible power utilization. Take additional steps to minimize total power consumption. This chapter describes recommended methods for measuring power and provides the recommended steps in detail to minimize overall power usage.
Page 44: Achieve Minimum Power Usage During All Power Modes
Ensure the USBC differential inputs (USBCP and USBCN) are pulled high or left floating with no impact to OTG pins. • Enable DC-DC internal power supply. • Ensure DC converter caps are connected properly. ® I:5-2 Intel PXA27x Processor Family Design Guide...
Page 45: Achieve Minimum Power Usage During Sleep
— Set auto power down (APD) bit. — Enable both instruction and data caches. — Use read allocate/write back (caching policy). • — Disable PLLs. • Idle — Ensure interrupts are disabled to prevent unexpected walk-ups. §§ ® Intel PXA27x Processor Family Design Guide I:5-3...
Page 46 Power Measurements ® I:5-4 Intel PXA27x Processor Family Design Guide...
Page 47: Introduction To Part Ii
Introduction to Part II The chapters in Part II of the Design Guide describe the design recommendations and constraints ® related to specific on-chip peripherals of Intel PXA27x Processor Family (PXA27x processor). These recommendations include information regarding signal connections, block diagrams, and notes related to system implementation.
Page 48 Introduction to Part II ® II:1-2 Intel PXA27x Processor Family Design Guide...
Page 49: Package And Pins
Package and Pins ® ® Refer to Intel PXA270 Processor Electrical, Mechanical, and Thermal Specification and Intel PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for complete information on processor signals, signal-to-package ball mapping, and package mechanical ® specifications for Intel PXA27x Family Processor (PXA27x processor).
Page 50 Package and Pins ® II:2-2 Intel PXA27x Family Processor Design Guide...
Page 51: Clocks And Power Interface
The GPIO<n> pins are used as standby and sleep wake-up sources. ® GPIO<n> Bidirectional For possible values for n, refer to the GPIO chapter in the Intel PXA27x Processor Family Developers Manual. GPIO<3> Bidirectional The GPIO<3> pin is used as standby, sleep, and deep-sleep wake-up sources.
Page 52: Power Manager Interface Control Signals
48 MHz output clock 48_MHz Clock Output Used to generate peripheral timing from the 312-MHz peripheral clock † Input and Output refers to signal direction to or from the PXA27x processor. ® II:3-2 Intel PXA27x Processor Family Design Guide...
Page 53: Nvdd_Fault
(using the mechanism selected by the PMCR[xIDEA] bits) until the SYS_DEL timer expires. The PXA27x processor also has a configuration bit that allows ® nVDD_FAULT to be ignored in sleep mode. Refer to Intel PXA270 Processor Electrical, ®...
Page 54: Nbatt_Fault
PXA27x processor from over-charging the backup battery. See Figure 3-1. This preventive action from D2 and R1 occurs if an input signal on the VCC_REG domain is driven above the backup battery voltage. ® II:3-4 Intel PXA27x Processor Family Design Guide...
Page 55 ALL_REGULATORS_OK Fault Monitor PWR_SCL nRESET PWR_SDA POW ER_SW ITCH PWR_SW_IN I2C_CLK GPIO0 LOGIC_VCC I2C_DATA GPIO1 ADAPTER_PWR PWR_SW_OUT VCC_BATT P ower Control Interface Fixed Regulator PW R_ADAPTER_DETECTED Main Battery B acku p Battery ® Intel PXA27x Processor Family Design Guide II:3-5...
Page 56: Layout Notes
13.000-MHz or a 32.768-KHz oscillator. Additionally, when the PXA27x processor generates either clock using its oscillator, this clock drives the clock inputs of other system components such as a cellular baseband processor. ® II:3-6 Intel PXA27x Processor Family Design Guide...
Page 57: Using The On-Chip Oscillator With A 32.768-Khz Crystal
® ® The Intel PXA270 Processor Electrical, Mechanical, and Thermal Specification and Intel PXA27x Processor Family Electrical, Mechanical, and Thermal Specification provide specifications for the 32.768-KHz crystal. To use the on-chip crystal oscillator, connect the 32.768- KHz crystal between the TXTAL_IN and TXTAL_OUT pins of the processor. The on-chip oscillator provides the required load capacitance, so do not connect external load capacitors to the crystal.
Page 58: Using An External 13.00-Mhz Clock
PXA27x Processor Family Electrical, Mechanical, and Thermal Specification. In systems which dynamically adjust the processor power supply and clock frequency to minimize power, there are ® additional requirements for the VCC_CORE power supply. Refer to the Intel PXA27x Processor Family Power Requirements Application Note document for more information.
Page 59 D+ and D- are out of compliance with the USB specification if VCC_USB is below 2.8 V. The +5 V V source from USB host controller, which is available for bus-powered peripherals, must be supplied from an external source. §§ ® Intel PXA27x Processor Family Design Guide II:3-9...
Page 60 Clocks and Power Interface ® II:3-10 Intel PXA27x Processor Family Design Guide...
Page 61: Internal Sram
The internal memory block has six major modules: • System Bus Interface • Control/Status Registers • Power Management • Memory Bank Muxing and Control • Queues • Four Memory Banks See the internal memory block diagram in Figure 4-1. ® Intel PXA27x Processor Family Design Guide II:4-1...
Page 62: Layout Notes
Bank 1 Bank 2 Bank 3 Power Management Memory Array ISRAM_001_P2 Layout Notes The power caps allows the internal SRAM to be powered up during sleep. Refer to Section 3.4 detailed information. §§ ® II:4-2 Intel PXA27x Processor Family Design Guide...
Page 63: Dma Controller Interface
DMA Controller Interface ® This chapter describes the procedures for interfacing the DMA controller of the Intel PXA27x Processor Family (PXA27x processor) with companion chips using the fly-by and flow-through DMA transfer. Overview The PXA27x processor contains a DMA controller that transfers data to and from the memory system in response to requests generated by peripherals or companion chips.
Page 64: Block Diagram
The DREQ<2:0> signals must remain asserted for four CLK_MEM cycles for the DMA to recognize the low to high transition. When de-asserted, the DREQ<2:0> signals must remain de- asserted for at least four CLK_MEM cycles. ® Refer to the Intel PXA270 Processor Electrical, Mechanical, and Thermal Specification and ® Intel PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for all AC timing information.
Page 65: Modes Of Operation
Requests on pins DREQ<1:0> are used for data transfers in fly-by mode. External Companion Chip Valid DVAL<1:0> Output The memory controller asserts DVAL to notify the companion chip that data must be driven or is valid. ® Intel PXA27x Processor Family Design Guide II:5-3...
Page 66: Block Diagram
Using fly-by DMA transfers, high-performance companion chips are directly connected to the data bus of the SDRAM devices. All companion chips are restricted to transfers whose alignment and length match those of the SDRAM devices. ® II:5-4 Intel PXA27x Processor Family Design Guide...
Page 67: Flow-Through Dma Transfers
DMA transfers. Figure 5-3. Companion Chip Requesting Flow-Through DMA Transfers PXA27x Processor Control Memory Control Signals Signals Memory Controller Controller Memory Devices (Static or MD<31:0> Dynamic) DREQx Companion Chip DMA_002_P2 ® Intel PXA27x Processor Family Design Guide II:5-5...
Page 68: Layout Notes
DMA Controller Interface 5.5.2.3 Layout Notes Refer to Section 5.4 for layout notes. §§ ® II:5-6 Intel PXA27x Processor Family Design Guide...
Page 69: System Memory Interface
System Memory Interface ® This chapter describes guidelines for interfacing with the memory controller of Intel PXA27x Processor Family (PXA27x processor) to external memory. See examples of schematics and timing diagrams for SDRAM, SRAM, flash, and PC Card devices. Overview The external memory bus interface for the PXA27x processor supports: •...
Page 70 (64 Mbytes max) (256 Mbytes max) SDRAM Bank 2 SDRAM Bank 2 0xA800_0000 0xA000_0000 (64 Mbytes max) (256 Mbytes max) SDRAM Bank 3 SDRAM Bank 3 0xAC00_0000 0xB000_0000 (64 Mbytes max) (256 Mbytes max) ® II:6-2 Intel PXA27x Processor Design Guide...
Page 71: Signals
0 = Wait 1 = VLIO is ready Boot Select signals – indicates the type of boot memory the system has Tied at board BOOT_SEL<0> Input level 0 = 32-bit ROM/flash 1 = 16-bit ROM/flash ® Intel PXA27x Processor Design Guide II:6-3...
Page 72 1 – Socket 1 NOTE: 1. The alternate function of the signal must be programmed to be accessed external of the PXA27x ® processor. Refer to the Intel PXA27x Processor Family Developers Manual on how to configure the alternate function. ®...
Page 73: Block Diagram
(16- or 32-bit wide) Static Bank 3 nCS<3> (up to 64MB) nCS<4> Static Bank 4 (up to 64MB) nCS<5> Static Bank 5 (up to 64MB) NOTE: Static Bank 0 must be populated by “bootable” memory ® Intel PXA27x Processor Design Guide II:6-5...
Page 74: Memory Controller Layout Notes
25 - 50 ohms 1 - 3 ns tolerance. 062 board Balanced-T 1 - 1.5” 0.5 - 0.75” 0.5 - 0.75” Code: 4-6 Note: Refer to Section 6.4.1.3 for information on board stack-up. ® II:6-6 Intel PXA27x Processor Design Guide...
Page 75: (Excludingsdclk And Sdcas)
Stripline with 60 Ω +15% Daisy Chain 5 - 6” 0.5” 20 ohms Code: 4-B tolerance. 062 board. Daisy Chain 5 - 6” 0.5” Note: Refer to Section 6.4.1.3 for information on board stack-up. ® Intel PXA27x Processor Design Guide II:6-7...
Page 76: Minimum Board Stack-Up Configuration Used For Signal Integrity
Pre Preg Er = 4.15 +/- 0.55 0.7 mils +/- 0.2 thick (031) (031, 062) Strip 1.4 mils +/- 0.2 thick (062) 5 mils +/- 1.5 width & E2E space (031, 062) Core Er = 4.15 +/- 0.55 ® II:6-8 Intel PXA27x Processor Design Guide...
Page 77: Modes Of Operation Overview
DQM<0> corresponds to MD<7:0> DQM<1> corresponds to MD<15:8> DQM<3:0> Output Active High DQM<2> corresponds to MD<23:16> DQM<3> corresponds to MD<31:24> 0 = Do not mask out corresponding byte 1 = Mask out corresponding byte ® Intel PXA27x Processor Design Guide II:6-9...
Page 78 Miscellaneous I/O Signals Data direction signal to be used by output transceivers RDnWR Output Active High 0 = MD<31:0> is driven by the PXA27x processor 1 = MD<31:0> is not driven by the PXA27x processor ® II:6-10 Intel PXA27x Processor Design Guide...
Page 79: Sdram Memory Block Diagram
SDRAM SDRAM SDRAM nRAS nRAS nRAS nCAS nCAS nCAS 21:10 21:10 21:10 addr<11:0> addr<11:0> addr<11:0> 23:22 23:22 23:22 BA<1:0> BA<1:0> BA<1:0> DQML DQML DQML DQMH DQMH DQMH 31:16 31:16 31:16 DQ<15:0> DQ<15:0> DQ<15:0> ® Intel PXA27x Processor Design Guide II:6-11...
Page 80: Sdram Layout Notes
For recommendations on trace lengths, size, and routing guidelines, refer to: • Part II: Section 6.4, “Memory Controller Layout Notes” ® For AC timing information, refer to Intel PXA270 Processor Electrical, Mechanical, and ® Thermal Specification and Intel PXA27x Processor Family Electrical, Mechanical, and Thermal Specification 6.5.1.3.1...
Page 81 8 M x 32 256 Mbit 2 x 13 x 8 16 M x 16 256 Mbit 2 x 13 x 9 32 M x 16 512 Mbit 2 x 13 x 10 ® Intel PXA27x Processor Design Guide II:6-13...
Page 82: Sa-1110 Address Compatibility Mode Memory Address Signal Mapping
32 M x 4 128 Mbit 2 x 12 x 11 8 M x 32 256 Mbit 2 x 13 x 8 16 M x 16 256 Mbit 2 x 13 x 9 ® II:6-14 Intel PXA27x Processor Design Guide...
Page 83: Flash Memory Interface (Asynchronous/Synchronous)
Flash Memory Interface (Asynchronous/Synchronous) Memory types are programmable through the memory interface configuration registers. Refer to ® the Intel PXA27x Processor Family Developers Manual for detail information on the configuration registers. Six chip selects control the static memory interface, nCS<5:0>. All the chip selects are configurable for non-burst ROM or flash memory, burst ROM or flash, SRAM, or SRAM-like variable latency I/O devices.
Page 84: Flash Block Diagram
Section 6.4 for recommendations on trace lengths, size, and routing guidelines. Refer to ® ® Intel PXA270 Processor Electrical, Mechanical, and Thermal Specification and Intel PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for AC timing information. ® II:6-16 Intel...
Page 85: Rom Interface
Miscellaneous I/O Signals Data direction signal to be used by output transceivers RDnWR Output Active High 0 = MD<31:0> is driven by the PXA27x processor 1 = MD<31:0> is not driven by the PXA27x processor ® Intel PXA27x Processor Design Guide II:6-17...
Page 86: Rom Block Diagram
Section 6.4 for recommendations on trace lengths, size, and routing guidelines. Refer to ® ® Intel PXA270 Processor Electrical, Mechanical, and Thermal Specification and Intel PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for AC timing information. 6.5.4 SRAM Interface For SRAM, DQM<3:0>...
Page 87: Sram Signals
Miscellaneous I/O Signals Data direction signal to be used by output transceivers RDnWR Output Active High 0 = MD<31:0> is driven by the PXA27x processor 1 = MD<31:0> is not driven by the PXA27x processor ® II:6-19 Intel PXA27x Processor Design Guide...
Page 88: Sram Block Diagram
Section 6.4 for recommendations on trace lengths, size, and routing guidelines. Refer to ® ® Intel PXA270 Processor Electrical, Mechanical, and Thermal Specification and Intel PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for AC timing information. ® II:6-20 Intel...
Page 89: Variable Latency Input/Output (Vlio) Interface
PXA27x processor. This is only valid VLIO memory. For more information, refer to the DMA ® chapter in the Intel PXA27x Processor Family Developers Manual. For writes to VLIO, if all byte enables are turned off (masking out the data DQM = 0b1111), then the write enable is suppressed (nPWE = 1) for this write beat to VLIO.
Page 90: Vlio Memory Signals
Miscellaneous I/O Signals Data direction signal to be used by output transceivers RDnWR Output Active High 0 = MD<31:0> is driven by the PXA27x processor 1 = MD<31:0> is not driven by the PXA27x processor ® II:6-22 Intel PXA27x Processor Design Guide...
Page 91: Vlio Block Diagram
Refer to ® ® Intel PXA270 Processor Electrical, Mechanical, and Thermal Specification and Intel PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for AC timing information. 6.5.6 PC Card (PCMCIA) Interface The PXA27x processor requires external glue logic to complete the 16-bit PC Card socket interface that allows either 1-socket or 2-socket solutions.
Page 92: Overview .........................................................................................................................I:
Note: If the system design incorporates PCMCIA interface, LCD and MSL (Baseband Interface), refer to Part II: Section 16.1, “Overview,” for important information on using these interfaces simultaneously. ® II:6-24 Intel PXA27x Processor Design Guide...
Page 93: Pc Card Signals
Miscellaneous I/O Signals Data direction signal used by output transceivers RDnWR Output Active High 0 = MD<31:0> is driven by the PXA27x processor 1 = MD<31:0> is not driven by the PXA27x processor ® II:6-25 Intel PXA27x Processor Design Guide...
Page 94: Pc-Card Block Diagrams
® ® Refer to Intel PXA270 Processor Electrical, Mechanical, and Thermal Specification and Intel PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for additional information. The weak (50 KΩ nominal) on-chip pull-downs are released when the RDH bit is cleared. Subsequently, contentions through the two board-level pull-ups occur only during PC- Card accesses.
Page 95: External Logic For A One-Socket Configuration Expansion Pc Card
GPIO<w> nCD<1> nPCD1 GPIO<x> nCD<2> PSKTSEL PRDY_BSY0 GPIO<y> RDY/nBSY PADDR_EN0 GPIO<z> MA<25:0> A<25:0> nPWE nPREG nREG nCE<2:1> nPCE<2:1> nPOE nIOR nPIOR nIOW nPIOW 5V to 3.3V nPWAIT nWAIT 5V to 3.3V nIOIS16 nIOIS16 ® II:6-27 Intel PXA27x Processor Design Guide...
Page 96: External Logic For A Two-Socket Configuration Expansion Pc Card
PSKTSEL A<25:0> MA<25:0> nREG nPREG A<25:0> nREG nCE<2:1>, nOE, nPCE<2:1>, nWE, nIOR, nPOE, nCE<2:1>, nOE, nIOW nPWE, nWE, nIOR, nPIOW, nIOW VCC_MEM nPIOR nWAIT VCC_MEM nPWAIT nWAIT VCC_MEM nIOIS16 VCC_MEM nIOIS16 nIOIS16 MEM_006_P2 ® II:6-28 Intel PXA27x Processor Design Guide...
Page 97: Pc Card Layout Notes
10 KΩ or greater in value. Refer to ® ® Intel PXA270 Processor Electrical, Mechanical, and Thermal Specification and Intel PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for the A/C timings information. Verify all signals are within the domain of their intended use. For example, some PC Card signals are on VCC_BB and some are on VCC_MEM.
Page 98 MBREQ an input. • Write the GPIO Alternate Function register (GAFR0_x) to set the bits that map the alternate functions on the specified GPIO pins to the Alternate Bus Master mode operation. ® II:6-30 Intel PXA27x Processor Design Guide...
Page 99: Alternate Bus Master Signals
Output enable for static memory NOTE: This signal is three-stated to be compatible with the Output High-Z Intel SA-1110 and must be driven by the alternate bus master during alternate bus master ownership Data direction signal to be used by output transceivers RDnWR...
Page 100: Alternate Bus Master Block Diagram
Alternate Bus Master Layout Notes Refer to Part II: Section 6.5.1.3, “SDRAM Layout Notes,” for recommendation on trace lengths, ® size, and routing guidelines. Refer to Intel PXA270 Processor Electrical, Mechanical, and ® Thermal Specification and Intel PXA27x Processor Family Electrical, Mechanical, and Thermal Specification documents for AC timing information.
Page 101 System Memory Interface ® II:6-33 Intel PXA27x Processor Design Guide...
Page 102 System Memory Interface ® II:6-34 Intel PXA27x Processor Design Guide...
Page 103: Lcd Interface
LCD Interface ® This chapter describes examples of hardware connections between Intel PXA27x Processor Family (PXA27x processor) and various types of Liquid Crystal Display (LCD) controllers. Active LCD displays, such as the Thin Film Transistor (TFT) display and passive LCD displays such as the Supertwist Nematic (STN) display, are discussed as well as single and dual-scan displays.
Page 104: Signals
Note: Not all signals are required for all modes of operation. Refer to the LCD panel reference documentation specific to the manufacturer for information on: • Specific signals required for correct LCD operation • Correct names of the signals used by the LCD panel manufacturer ® II:7-2 Intel PXA27x Processor Family Design Guide...
Page 105: Schematics/Block Diagram
LCD panel to determine the variable voltage circuit design. Ensure the contrast voltage is stable; unstable voltage causes visual artifacts. Possible contrast-voltage circuits are often suggested by panel manufacturers. ® II:7-3 Intel PXA27x Processor Family Design Guide...
Page 106: Backlight Inverter
When laying out your design, minimize trace length of the LCD panel signals and allow sufficient spacing between signals to avoid crosstalk. Crosstalk decreases the signal integrity, especially the data line signals. ® II:7-4 Intel PXA27x Processor Family Design Guide...
Page 107: Panel Connector
There are other factors related to choosing a refresh rate for an LCD system, most significant is the impact on ® system bandwidth. Refer to the section on “Bandwidth Calculations” in the Intel PXA27x Processor Family Developers Manual for more information.
Page 108: Modes Of Operation Overview
Similarly, not all signals are required for all modes of operation. Refer to the LCD panel reference documentation for information on: • Specific signals required for correct LCD operation • Correct names of the signals used by the LCD panel manufacturer ® II:7-6 Intel PXA27x Processor Family Design Guide...
Page 109: Schematics/Block Diagram
Figure 7-1. Passive Monochrome Single-Scan Display Typical Connection LDD<0> Top Left LDD<1> LDD<2> LDD<3> L_PCLK_WR PIXEL_CLOCK L_LCLK_A0 LINE_CLOCK L_FCLK_RD FRAME_CLOCK L_BIAS BIAS 7.5.1.3 Layout Notes Refer to Section 7.4, “Layout Notes,” for layout notes and considerations. ® II:7-7 Intel PXA27x Processor Family Design Guide...
Page 110: Passive Monochrome Single-Scan Double-Pixel Mode
Similarly, not all signals are required for all modes of operation. Refer to the LCD panel reference documentation for information on: • Specific signals required for correct LCD operation • Correct names for the signals used by the LCD panel manufacturer ® II:7-8 Intel PXA27x Processor Family Design Guide...
Page 111: Layout Notes
Pixel Clock – used by the LCD display to clock the pixel data into the L_PCLK_WR Pixel_Clock Output line shift register. ® II:7-9 Intel PXA27x Processor Family Design Guide...
Page 112: Schematics / Block Diagram
Top Left of "Upper Panel" DU_0 LDD<1> DU_1 LDD<2> DU_2 LDD<3> DU_3 LDD<4> Top Left of "Lower Panel" DL_0 LDD<5> DL_1 LDD<6> DL_2 LDD<7> DL_3 L_PCLK_WR PIXEL_CLOCK L_LCLK_A0 LINE_CLOCK L_FCLK_RD FRAME_CLOCK L_BIAS BIAS ® II:7-10 Intel PXA27x Processor Family Design Guide...
Page 113: Layout Notes
Similarly, not all signals are required for all modes of operation. Refer to the LCD panel reference documentation for information on: • Specific signals required for correct LCD operation • Correct names of the signals used by the LCD panel manufacturer ® II:7-11 Intel PXA27x Processor Family Design Guide...
Page 114: Schematics/Block Diagram
7.5.5.1 Signals For passive color dual-scan displays, see Table 7-7 for description of the pins required for connections between the PXA27x processor and LCD panel. ® II:7-12 Intel PXA27x Processor Family Design Guide...
Page 115: Passive Display Pins Required
Similarly, not all signals are required for all modes of operation. Refer to the LCD panel reference documentation for information on: • Specific signals required for correct LCD operation • Correct names of the signals used by the LCD panel manufacturer ® II:7-13 Intel PXA27x Processor Family Design Guide...
Page 116: Active Color 12-Bit Per Pixel Mode
PXA27x processor in 16 bpp, but only connecting a subset of the data lines. 7.5.6.1 Signals The signals described in Table 7-8 implement an active color 12-bit per pixel display with the PXA27x processor. ® II:7-14 Intel PXA27x Processor Family Design Guide...
Page 117: Schematics / Block Diagram
The sample below shows four red, four green, and four blue bits on the LCD panel. However, different active display panels might have more or different data lines. Consult the LCD panel manufacturer’s documentation for the actual data lines. ® II:7-15 Intel PXA27x Processor Family Design Guide...
Page 118: Layout Notes
LCCR0[LDDALT] to avoid any issues associated with the implementation of the overlays. Refer to the description of the LCD Controller Control Register 0 in Section 7.5, “LCD Control ® Registers,” of the Intel PXA27x Processor Family Developers Manual for more information. ®...
Page 119: Signals
The example below shows five red, six green, and five blue bits on the LCD panel. However, different active display panels might have more or different data lines. Consult the LCD panel manufacturer’s documentation for the actual data lines. ® II:7-17 Intel PXA27x Processor Family Design Guide...
Page 120: Layout Notes
Note: If the system design incorporates PCMCIA interface, LCD and MSL (Baseband Interface), refer to Part II, Section 16.1, “Overview,” for important information on using these interfaces simultaneously. ® II:7-18 Intel PXA27x Processor Family Design Guide...
Page 121: Signals
The example below shows six red, six green, and six blue bits on the LCD panel. However, different active display panels might have more or different data lines. Consult the LCD panel manufacturer’s documentation for the actual data lines. ® II:7-19 Intel PXA27x Processor Family Design Guide...
Page 122: Layout Notes
Note: The interface only uses eight data pins (LDD<7:0>). Therefore, three clock cycles transmit one pixel of information to the panel. Refer to the display manufacturer’s documentation for information on how data is transmitted to the display. ® II:7-20 Intel PXA27x Processor Family Design Guide...
Page 123: Signals
Schematics / Block Diagram Figure 7-9 for illustration of typical connections for a smart panel. The sample connections serve as a guide for designing systems that contain LCD displays with embedded frame-buffer memory. ® II:7-21 Intel PXA27x Processor Family Design Guide...
Page 124: Layout Notes
LDD<2> LDD<3> LDD<4> LDD<5> LDD<6> LDD<7> MSB L_PCLK_WR WRITE L_LCLK_A0 COMMAND L_FCLK_RD READ L_CS SELECT L_VSYNC SYNC 7.5.9.3 Layout Notes Refer to Section 7.4, “Layout Notes,” for layout notes and considerations. §§ ® II:7-22 Intel PXA27x Processor Family Design Guide...
Page 125: Ssp Port Interface
Two of the SSPs are configurable in any of the modes described in this chapter; the third is configurable for any mode except external clocking. ® Refer to chapter 8 of the Intel PXA27x Processor Family Developers Manual for information on programming and configuring the SSPs. This chapter only describes the physical connections for the SSPs.
Page 126: Signals
Table 8-1. Refer to the GPIO Alternate ® Function table in the GPIO chapter of the Intel PXA27x Processor Family Developers Manual for the GPIO assignments of the SSP signals. Table 8-1. SSP Serial Port I/O Signals (Sheet 1 of 2)
Page 127: Block Diagram
SSPSCLK2. This function is multiplexed with other alternate functions. Refer to Chapter 24, “General Purpose I/O Controller,” SSPSCLK2EN Input ® the Intel PXA27x Processor Family Developers Manual . SSPSCLK2EN is multiplexed with the SSPEXTCLK2 alternate function (refer to Chapter 24, “General-Purpose I/O Controller”).
Page 128: External Clock Source Configuration Scheme
SSP Port Interface Figure 8-1. Standard SSP Configuration Scheme Block Diagram SSPSCLK SSPSFRM SSPRXD ® Peripheral SSP Intel PXA27x Processor SSPTXD SSPCLKEN/ SSPEXTCLK 8.3.2 External Clock Source Configuration Scheme The external clock source configuration allows for an external clock source to be the SSPCLK generation source.
Page 129: External Clock Enable Configuration Scheme
Figure 8-3 for illustration of the physical connection of the external clock enable configuration. Figure 8-3. External Clock Enable Configuration Scheme Block Diagram SSPSCLK SSPSFRM ® Intel PXA27x Processor SSPRXD Peripheral SSP SSPTXD SSPCLKEN Clock Enable from External Source 8.3.4...
Page 130: Layout Notes
SSP Port Interface Figure 8-4. Internal Clock Enable Configuration Scheme Block Diagram ® Intel PXA27x Processor SSPSFRM SSPRXD Peripheral SSP #2 SSP2 SSPTXD SSP2SCLK tx_not_empty2 This page intentionally left blank. SSP2SCLK SSPSFRM SSP1 SSPRXD Peripheral SSP #1 SSPTXD Layout Notes The tested maximum switching speed of the SSPs is 13 MHz.
Page 131: Overview
Inter-Integrated Circuit (I Overview ® The Inter-Integrated Circuit (I C) bus interface unit allows Intel PXA27x Processor Family (PXA27x processor) to serve as a master and slave device residing on the I C bus. The I C bus is a serial bus developed by the Philips Corporation consisting of a two-pin interface.
Page 132: Schematic/Block Diagram
I C bus interface unit. The DAC modifies the voltage of the feedback path that affects the processor core voltage. Figure 9-1. Linear Technology DAC with I C Interface 1ΜΩ Vout LTC1663C35 ® II:9-2 Intel PXA27x Processor Family Design Guide...
Page 133: Other Uses Of I2C
Note: The CF card socket is disabled if a device is inserted in the expansion bus. Figure 9-2. Using an Analog Switch to Allow a Second CF Card COM_1 NC_2 CF_I2C_SCL I2C_ENAB IN_7 MAX4547 IN_2 CF_I2C_SDA COM_7 NC_1 ® II:9-3 Intel PXA27x Processor Family Design Guide...
Page 134: Pull-Ups And Pull-Downs
Separate the physical routing of the data and clock signals and ensure that lines are not routed near other potential noise sources, such as switching regulators or signals with high switching frequencies. §§ ® II:9-4 Intel PXA27x Processor Family Design Guide...
Page 135: Uart Interfaces
UART Interfaces This chapter describes guidelines to interface to the Universal Asynchronous Receiver/Transmitter ® (UART) serial ports of Intel PXA27x Processor Family (PXA27x processor). 10.1 Overview The PXA27x processor has three UARTs: • A Full Function UART (FFUART) • A Bluetooth UART (BTUART) •...
Page 136: Signals
MSR. nDCD has no effect on the receiver. This signal is present only on the FFUART. When the DCD bit changes state and the Modem Status interrupt is enabled, an interrupt is generated. ® II:10-2 Intel PXA27x Processor Family Design Guide...
Page 137: Types Of Uarts
Full Function UART Data Set Ready FFDCD Input Full Function UART Data Carrier Detect FFRI Input Full Function UART Ring Indicator FFDTR Output Full Function UART Data Terminal Ready FFRTS Output Full Function UART Request to Send ® II:10-3 Intel PXA27x Processor Family Design Guide...
Page 138: Ffuart Block Diagram
FFDTR FFRI UART_001_P2 10.3.1.3 FFUART Layout Notes The RS-232 transceiver device converts CMOS logic voltage levels to RS-232 standard line voltage levels. Locate the RS-232 transceiver close to the 9-pin DIN connector. ® II:10-4 Intel PXA27x Processor Family Design Guide...
Page 139: Bluetooth Uart
Bluetooth module connector. The block diagram demonstrates high level signal usage and connectivity when using the BTUART. Figure 10-2. BTUART Interface Block Diagram PXA27x Processor BTUART BTRXD Bluetooth BTRTS Module BTTXD Connector BTCTS UART_002_P2 ® II:10-5 Intel PXA27x Processor Family Design Guide...
Page 140: Standard Uart
STUART. Figure 10-3. STUART Interface Block Diagram PXA27x Processor STUART IrDA Transceiver STD_RXD STD_TXD Transceiver Enable and Speed CONTROL Control Signals, that is, from SIGNALS FPGA, CPLD, or PXA27x GPIOs UART_003_P2 §§ ® II:10-6 Intel PXA27x Processor Family Design Guide...
Page 141: Fast Infrared Interface
Fast Infrared Interface Fast Infrared Interface This chapter describes guidelines for interfacing with the external LED transceivers to fast infrared ® (FIR) controller of Intel PXA27x Processor Family (PXA27x processor). 11.1 Overview The Fast Infrared Communications Port (FICP) operates at half-duplex and provides direct connection to commercially available Infrared Data Association (IrDA) compliant LED transceivers.
Page 142: Block Diagram
Figure 11-1. Fast Infrared Controller Port Interface Block Diagram PXA27x Processor IrDA Transceiver FICP Controller ICP_TXD ICP_RXD Transceiver Enable and Speed CONTROL Control Signals, that is, from SIGNALS FPGA, CPLD, or PXA27x GPIOs FIR_001_P2 §§ ® II:11-2 Intel PXA27x Processor Family Design Guide...
Page 143: Usb Client Controller
This chapter describes guidelines to interface the Universal Serial Bus (USB) Client Controller of ® Intel PXA27x Processor Family (PXA27x processor) to a USB client cable connector for attachment to a USB network. Included in this chapter is a description of how to connect the PXA27x processor single-ended USB Host and USB On-The-Go (OTG) ports to external components.
Page 144: Block Diagram
USB cable, 90 Ω , without the use of external series resistors. The 0 Ω resistors are optional and are installed if series resistors are necessary to compensate for minor differences between the USB cable and the board trace impedances. ® II:12-2 Intel PXA27x Processor Family Design Guide...
Page 145: Operation If Gpion And Gpiox Are Different Pins
This results in USB D+ being pulled high using the 1.5 K Ω resistor to indicate to the host controller that a fast USB client device is connected per the Universal Serial Bus Specification, Revision 1.1. ® Intel PXA27x Processor Family Design Guide II:12-3...
Page 146: Operation If Gpion And Gpiox Are The Same Pin
Controller Cable Connector GPIOn 3.3V VBUS (+5V) 1.5K Board Ground Note 1 0 Ohm USBC_P USB D+ 0 Ohm USBC_N USB D- Note 1: Some designs use the internal pull-up resistor. USBC_003_P2 ® II:12-4 Intel PXA27x Processor Family Design Guide...
Page 147: Bus-Powered Device
500 µA unless it enters sleep or deep sleep mode. If it enters either of these reduced power modes, all USB registers are reset and the USB client does not respond to its host-assigned address. ® Intel PXA27x Processor Family Design Guide II:12-5...
Page 148: Usb On-The-Go Transceiver Usage
As shown in Figure 12-5, SW1 on the D+ pad is enabled and SW1 on the D- pad is disabled when host port 2 is being used for USB device controller data. ® II:12-6 Intel PXA27x Processor Family Design Guide...
Page 149 Note: There are programming requirements for disabling and enabling the transceiver and pull-up/pull- ® down resistors for USB host port 2 and for sleep and standby mode operation. Refer to the Intel PXA27x Processor Family Developers Manual for additional information.
Page 150: Interface To External Transceiver (Otg)
USB Device Controller D+/D- USB_P2_2 Transmit enable Dat_VP OE_Tp_Int_N SE0_VM Suspend Enable UP2OCR[EXSUS] Vbus Vbus Speed Control UP2OCR[EXSP] USB_P2_8 Interrupt Ext. Trans. Interrupt External OTG UP2OCR[SEOS] Transceiver USB_P2_7 USB_P2_1 OTG ID PXA27x Processor ® II:12-8 Intel PXA27x Processor Family Design Guide...
Page 151: Interface To External Charge Pump Device (Otg)
“USB Port 2 Output Control Register (UP2OCR)” provides inputs to interface to the external charge pump device: • Vbus valid 4.0 • Vbus valid 4.4 • Session valid • Session request protocol (SRP) detected interrupt ® Intel PXA27x Processor Family Design Guide II:12-9...
Page 152 Session Valid USB_P2_8 UP2OCR[HXOE] External Charge Pump UP2OCR[CPVEN] UP2OCR[CPVPE] USB_P2_5 Vbus Valid 4.0 V Vbus Valid 4.4 V USB_P2_3 SRP Detect Session Valid USB_P2_1 UP2OCR[SE0S] OTG ID USB_P2_2 USB_P2_7 OTG ID PXA27x Processor ® II:12-10 Intel PXA27x Processor Family Design Guide...
Page 153: Otg Id
U P 2 O C R [ I D E N ] O T G I D 1 0 O h m P X A 2 7 x P r o c e s s o r ® Intel PXA27x Processor Family Design Guide II:12-11...
Page 154: Interface To External Usb Transceiver (Non-Otg)
Figure 12-9. PXA27x Processor Connection to External USB Transceiver USB Host USB_P2_4 Controller SPEED Transmit enable OE_n USB_P2_6 USB Device Controller D +/D - USB_P2_7 UP2OCR[EXSP] USB_P2_2 Transmit enable UP2OCR[SE0S] USB_P2_1 USB_P2_5 External USB USB_P2_3 Transceiver PXA27x Processor ® II:12-12 Intel PXA27x Processor Family Design Guide...
Page 155 Table 12-3. Output to External USB Transceiver P2_6/P3_6 P2_4/P3_4 Result Logic “0” “SE0” Logic “1” “SE0” Table 12-4. Input from External USB Transceiver P2_5/P3_5 P2_3/P3_3 Result “SE0” Low Speed Full Speed Error §§ ® Intel PXA27x Processor Family Design Guide II:12-13...
Page 156 ‘USB Client Controller ® II:12-14 Intel PXA27x Processor Family Design Guide...
Page 157: Overview
AC ’97 ® This chapter describes guidelines to interface the AC ‘97 controller of Intel PXA27x Processor Family (PXA27x processor) to an external CODEC device. 13.1 Overview The AC ’97 controller unit connects external audio integrated circuit devices and CODECs to the PXA27x processor.
Page 158: Block Diagram
Primary Codec AC97_SDATA_OUT SDATA_OUT AC97_SYNC (48 kHz) SYNC AC97_SDATA_IN_0 SDATA_IN AC97_SDATA_IN_1 AC97_BITCLK (12.288 MHz) AC97_BITCLK (12.288 MHz) BIT_CLOCK AC97_SYSCLK (Optional) (24.5 MHz) AC ‘97 nRESET Secondary Codec SDATA_OUT SYNC SDATA_IN BIT_CLOCK AC97_001_P2 ® II:13-2 Intel PXA27x Processor Family Design Guide...
Page 159: Layout Notes
4. Set the level of GPIO[113] to output high during sleep mode by setting the Power Manager GPIO Sleep-State register, PGSR3[SS113] bit. ® 5. Enter sleep mode as outlined in Section 3 of the Intel PXA27x Processor Family Developer’s Manual.
Page 160 The optional AC97_SYSCLK output is used for clocking the AC ‘97’s XTL_IN input, instead of using an external oscillator (or external crystal). This option offers part count, cost, and PCB space saving opportunities for the system designer. §§ ® II:13-4 Intel PXA27x Processor Family Design Guide...
Page 161: I2S Interface
S Interface ® This chapter describes guidelines to interface the Inter IC Sound (I S or IIS) controller of Intel PXA27x Processor Family (PXA27x processor) to an external CODEC device. 14.1 Overview S is the name of a protocol defined by Philips Semiconductor for transferring two-channel digital audio signals (digital stereo audio) from one IC device to another.
Page 162: Signals
The state of SYNC denotes whether the current serial data samples are left or right channel data. SDATA_OUT Output Serial audio output data to CODEC SDATA_IN Input Serial audio input data from CODEC ® II:14-2 Intel PXA27x Processor Family Design Guide...
Page 163: Block Diagram
Fill the areas between analog traces with copper tied to the analog ground. Fill the regions between digital traces with copper tied to the digital ground. • Locate the decoupling capacitors for the analog portion as close to the CODEC as possible. ® Intel PXA27x Processor Family Design Guide II:14-3...
Page 164: Modes Of Operation Overview
SYSCLK must be configured as an output Left/Right identifier SYNC Output SYNC is BITCLK divided by 64 SDATA_OUT Output Serial audio output data to CODEC SDATA_IN Input Serial audio input data from CODEC ® II:14-4 Intel PXA27x Processor Family Design Guide...
Page 165 CODEC device when the PXA27x processor provides BITCLK to the CODEC. Figure 14-2. PXA27x Processor Provides BITCLK PXA27x Processor S Controller Program PLL Clock Divisor S CODEC SYSCLK CLOCK Divide by BITCLK BITCLK Divide by SYNC SYNC SDATA_OUT DAC_DATA SDATA_IN ADC_DATA I2S_002_P2 ® Intel PXA27x Processor Family Design Guide II:14-5...
Page 166: Block Diagram
CODEC device when the PXA27x processor receives BITCLK from the CODEC. Figure 14-3. PXA27x Processor Receives BITCLK PXA27x S Codec Processor External Clock CLOCK SYSCLK Source S Controller BITCLK BITCLK Divide by SYNC SYNC SDATA_OUT DAC_DATA SDATA_IN ADC_DATA I2S_003_P2 §§ ® II:14-6 Intel PXA27x Processor Family Design Guide...
Page 167: Multimediacard/Sd/Sdio Card Controller
MultiMediaCard/SD/SDIO Card Controller This chapter describes guidelines to interface the MultiMediaCard (MMC)/SD/SDIO controller of ® Intel PXA27x Processor Family to MMC/SD/SDIO sockets for use with MMC, SD, and SDIO card devices. 15.1 Overview The MMC/SD/SDIO controller performs the following tasks: •...
Page 168: Layout Notes
MMC socket MMC device Table 15-3 for the list of maximum number of memory devices supported for the different operating modes and communication protocols of the MMC/SD/SDIO controller of the PXA27x processor. ® II:15-2 Intel PXA27x Processor Family Design Guide...
Page 169 The system designer determines whether to implement a dedicated regulator or pass-transistor for supplying 3.3 V to the MMC/SD/SDIO socket. The decision is based upon analysis of functionality versus component/board real estate costs. ® Intel PXA27x Processor Family Design Guide II:15-3...
Page 170: Modes Of Operation Overview
Multimedia Card Protocol Interface Signals Signal Direction Description Name (MMC Protocol) MMCLK Output MMC bus clock MMCMD Bidirectional Bidirectional signal for MMC command and response tokens MMDAT<0> Bidirectional Bidirectional signal for MMC read and write data ® II:15-4 Intel PXA27x Processor Family Design Guide...
Page 171: Mmc Protocol Block And Schematic Diagrams
MMC communication protocol with MMC devices. Figure 15-1. MMC Protocol Interface Block Diagram PXA27x Processor MMC/SD/SDIO Controller (MMC Protocol) MMC Stack Clock MMCLK Command MMCMD Response Write Data MMDAT<0> Read Data MMDAT<1> MMDAT<2>/ MMCCS<0> MMDAT<3>/ MMCCS<1> MMC_001_P2 ® Intel PXA27x Processor Family Design Guide II:15-5...
Page 172: Mmc Protocol Layout Notes
MMC device with an SD/SDIO Card socket; MMDAT<1> and MMDAT<2> are not used as the MMC device does not have physical contacts to interface to these SD/SDIO Card socket signals. ® II:15-6 Intel PXA27x Processor Family Design Guide...
Page 173: Mmc/Sd/Sdio Mode Using Sd Or Sdio Protocols
Bidirectional signal for SD/SDIO 4-bit data transfers and to MMDAT<1> Bidirectional signal SDIO interrupts to the controller MMDAT<2>/MMCCS<0> Bidirectional Bidirectional signal for SD/SDIO 4-bit data transfers only MMDAT<3>/MMCCS<1> Bidirectional Bidirectional signal for SD/SDIO 4-bit data transfers only ® Intel PXA27x Processor Family Design Guide II:15-7...
Page 174: Sd And Sdio Protocol Block And Schematic Diagrams
Response Write Data MMDAT<0> DAT0 Read Data 4-bit Write Data MMDAT<1> DAT1 4-bit Read Data 4-bit Write Data MMDAT<2>/MMCCS<0> DAT2 4-bit Read Data 4-bit Write Data MMDAT<3>/MMCCS<1> DAT3 4-bit Read Data MMC_002_P2 ® II:15-8 Intel PXA27x Processor Family Design Guide...
Page 175 CPLD/GPIO Card Detect Debounce Circuitry to CPLD/GPIO 3.3V 100K 100K 3.3V COMM SD/SDIO MMDAT<1> DAT1 Card Socket MMDAT<0> DAT0 VSS2 MMCLK 3.3V 3.3V 0.1 uF VSS1 MMCMD MMDAT<3>/MMCCS<1> DAT3_CD MMDAT<2>/MMCCS<0> DAT2 MMC_007_P2 ® Intel PXA27x Processor Family Design Guide II:15-9...
Page 176: Sd And Sdio Protocol Layout Notes
SD/SDIO Card device insertion occurred. To wake up the PXA27x processor from sleep mode using this technique, a GPIO input signal capable of waking up the processor must be ® selected. Refer to the Intel PXA27x Processor Family Developers Manual for details on configuring GPIOs and GPIO sleep wake-up capabilities.
Page 177: Spi Mode With Mmc, Sd Card, And Sdio Card Devices
Input for SPI response token and read data MMDAT<1> Input Input to signal SDIO interrupts to the controller MMDAT<2>/ MMCCS<0> Output SPI CS0 chip select MMDAT<3>/ MMCCS<1> Output SPI CS1 chip select ® Intel PXA27x Processor Family Design Guide II:15-11...
Page 178: Spi Protocol Block And Schematic Diagrams
SPI mode operation. MMCCS<0> and MMCCS<1> are used as chip selects only in SPI mode and connect separately to the respective chip select signals of the socket. §§ ® II:15-12 Intel PXA27x Processor Family Design Guide...
Page 179: Baseband Interface
PXA27x Processor Family (PXA27x processor) and a cellular baseband processor. PXA27x processor provides a high performance, scalable baseband interface to Intel baseband processors described in a later revision of this document. However, PXA27x processor also provides other standard peripheral interfaces that support connection to a number of wireless baseband subsystems from other manufacturers.
Page 180 Baseband Interface ® II:16-2 Intel PXA27x Processor Family Design Guide...
Page 181: Memory Stick Host Interface
The memory stick signals are implemented through the GPIOs of the PXA27x processor. Refer to ® GPIO alternate function table in the GPIO section of the Intel PXA27x Processor Family Developers Manual for the GPIO assignments of the memory stick signals.
Page 182 The Sony Memory Stick Standard, Format Specification Version 1.3 requires that when a memory stick is inserted VSS is the first pin to make contact. The specification also requires INS to be the last pin to make contact upon insertion. §§ ® II:17-2 Intel PXA27x Processor Family Design Guide...
Page 183: Keypad Interface
Keypad Interface ® This chapter describes the procedures for interfacing with the keypad controller of Intel PXA27x Processor Family (PXA27x processor). 18.1 Overview The keypad interface block provides an interface to two styles of keypads: direct key and matrix key, and supports both types of keypads simultaneously.
Page 184: Signals
Key Debounce Interval and the automatic scan on activity bit (ASACT) of the KPC is set. In the Manual Scan mode, the scan signals are specified in the KPC register. ® II:18-2 Intel PXA27x Processor Family Design Guide...
Page 185: Block Diagram
KP_DKIN<4> Interface KP_DKIN<5> KP_DKIN<6> KP_DKIN<7> KP_MKOUT<7> KP_MKOUT<6> KP_MKOUT<5> KP_MKOUT<4> KP_MKOUT<3> KP_MKOUT<2> KP_MKOUT<1> KP_MKOUT<0> KP_MKIN<0> Keypad KP_MKIN<1> Interface Registers KP_MKIN<2> KP_MKIN<3> KP_MKIN<4> KP_MKIN<5> KP_MKIN<6> KP_MKIN<7> Matrix Interface Matrix Keypad Keypad Interface Controller KEYPAD_001_P2 ® Intel PXA27x Processor Family Design Guide II:18-3...
Page 186: Layout Notes
PXA27x processor package, a value of zero is read in and the input is not left floating. Leaving the input floating causes excessive use of power. ® II:18-4 Intel PXA27x Processor Family Design Guide...
Page 187: Interfacing To A Matrix Keypad
Keypad Control register as 8 (KPC[DKN] = “111”), a logic 0 on direct key inputs 2 and 3 is guaranteed and no activity is detected on them. ® For details about GPIO configuration, refer to the GPIO section of the Intel PXA27x Processor Family Developers Manual.
Page 188: Modes Of Operation Overview
4 x 4 matrix keypad of 16 keys, 8 direct keys with no rotary encoder. 18.5.1.1 Signals The signal definitions do not change, just the signal usage. See Figure 18-2 for detailed signal information. ® II:18-6 Intel PXA27x Processor Family Design Guide...
Page 189: Block Diagram
KP_MKOUT<7> KP_MKOUT<6> KP_MKOUT<5> KP_MKOUT<4> Matrix KP_MKOUT<3> Scan KP_MKOUT<2> KP_MKOUT<1> KP_MKOUT<0> KP_MKIN<0> Keypad KP_MKIN<1> Interface Registers KP_MKIN<2> KP_MKIN<3> Matrix Sense KP_MKIN<4> Matrix Keypad (4x4) KP_MKIN<5> KP_MKIN<6> KP_MKIN<7> Matrix Interface Keypad Interface Controller KEYPAD_002_P2 ® Intel PXA27x Processor Family Design Guide II:18-7...
Page 190: Keypad Matrix And Direct Keys With One Rotary Encoder
3 x 4 matrix keypad of 12 keys, 6 direct keys, and 1 rotary encoder. 18.5.2.1 Signals The signal definitions do not change, just the signal usage. See Figure 18-3 for detailed signal information. ® II:18-8 Intel PXA27x Processor Family Design Guide...
Page 191: Block Diagram
KP_MKOUT<7> KP_MKOUT<6> KP_MKOUT<5> KP_MKOUT<4> Matrix KP_MKOUT<3> Scan KP_MKOUT<2> KP_MKOUT<1> KP_MKOUT<0> KP_MKIN<0> Keypad KP_MKIN<1> Interface Registers KP_MKIN<2> KP_MKIN<3> Matrix Sense KP_MKIN<4> Matrix Keypad (3x4) KP_MKIN<5> KP_MKIN<6> KP_MKIN<7> Matrix Interface Keypad Interface Controller KEYPAD_003_P2 ® Intel PXA27x Processor Family Design Guide II:18-9...
Page 192: Keypad Matrix And Direct Keys With Two Rotary Encoders
18.5.3.1 Signals The signal definitions do not change, just the signal usage. See Figure 18-4 for detailed signal information. ® II:18-10 Intel PXA27x Processor Family Design Guide...
Page 193: Block Diagram
KP_MKOUT<7> KP_MKOUT<6> KP_MKOUT<5> KP_MKOUT<4> Matrix KP_MKOUT<3> Scan KP_MKOUT<2> KP_MKOUT<1> KP_MKOUT<0> KP_MKIN<0> Keypad KP_MKIN<1> Interface Registers KP_MKIN<2> KP_MKIN<3> Matrix Sense KP_MKIN<4> Matrix Keypad (4x4) KP_MKIN<5> KP_MKIN<6> KP_MKIN<7> Matrix Interface Keypad Interface Controller KEYPAD_004_P2 ® Intel PXA27x Processor Family Design Guide II:18-11...
Page 194 Keypad Interface §§ ® II:18-12 Intel PXA27x Processor Family Design Guide...
Page 195: Usim Controller Interface
USIM Controller Interface ® This chapter describes the universal subscriber identity module (USIM) of Intel PXA27x Processor Family (PXA27x processor) controller interface guidelines. 19.1 Overview The USIM controller is an interface for a GSM mobile handset. The USIM interface supports communication with smart cards as specified in ISO standard 7816-3 and technical specification 3G TS 31.101 of the 3rd Generation Partnership Project.
Page 196: Signals
This signal connects directly to the card CLK signal. The card cannot use any other clock. Reset signal to card nURST Output The card is reset when this output is asserted UDET Output USIM Detection for card present Output USIM Enable for VCC_USIM connection II:19-2 Intel® PXA27x Processor Family Design Guide...
Page 197: Usim Card Interface Signals
Power Manager USIM Card Control/Status ® Register (PUCR) in the Clocks and Power Manager Unit chapter of the Intel PXA27x Processor Family Developers Manual . 3. Voltage level of pads is set off chip. The pads work at either 1.8 V or 3.0 V.
Page 198: Block Diagram
Section 3.8.1.15, “Power Manager USIM Card Control/Status Register (PUCR),” in the ® Clocks and Power Manager Unit section of the Intel PXA27x Processor Family Developers Manual for information on control/status programmability. Figure 19-1. Connectivity USIM Card and PXA27x Processor USIM Interface using UVSx...
Page 199: Layout Notes
To prevent these electrical problems, turn off the external power supply before (or at the same time) the PXA27x processor enters deep sleep mode and correctly configures GPIOs prior to entering deep sleep mode. §§ Intel® PXA27x Processor Family Design Guide II:19-5...
Page 200 USIM Controller Interface II:19-6 Intel® PXA27x Processor Family Design Guide...
Page 201: Universal Serial Bus Host Interface
Universal Serial Bus Host Interface This chapter describes guidelines for: ® • Interfacing the Universal Serial Bus (USB) host controller of the Intel PXA27x Processor Family (PXA27x processor) to a USB host cable connector • Attaching USB client devices to the USB host controller of the PXA27x processor 20.1...
Page 202: Block Diagrams
Switch Circuitry (Required) USBHPWR<1> FAULT USBH_P<1> USB D+ Termination, Filtering, and ESD Protection Circuitry (Optional) USBH_N<1> USB D- = 68 - 75 pF = 10 - 25 Ohms USBH_001_P2 = 15K Ohms ® II:20-2 Intel PXA27x Processor Family Design Guide...
Page 203: Block Diagrams For Usb Host Port 2 (Differential Or Single-Ended)
U SB_P2_6 USB Device C ontroller D +/D - U SB_P2_7 U P2O C R[EXSP] U SB_P2_2 Transm it enable U P2O CR [SE0S] USB_P2_1 USB_P2_5 External USB USB_P2_3 Transceiver PXA27x Processor ® Intel PXA27x Processor Family Design Guide II:20-3...
Page 204: Block Diagram For Usb Host Single-Ended Connection (Port 3)
Note: The “SPEED” signal does not exist for PXA27x Host Port 3. The “SPEED” signal of the external device must be tied high or low. The system designer must program PXA27x Host 3 to match the external device speed. ® II:20-4 Intel PXA27x Processor Family Design Guide...
Page 205: Layout Notes
USBH_P<3:1> and USBH_N<3:1> are differential pair signals. Use these recommended layout guidelines: • Route the signals close to each other as parallel traces on the PCB. • Match the trace lengths as closely as possible (within ±0.5 inches (12.7 mm)). §§ ® II:20-5 Intel PXA27x Processor Family Design Guide...
Page 206 Universal Serial Bus Host Interface ® II:20-6 Intel PXA27x Processor Family Design Guide...
Page 207: Real Time Clock Interface
1.0 Hz output signal. The ® configuration of the RTC is accomplished through software and is described in details in the Intel PXA27x Processor Family Developers Manual. The RTC signal is implemented through the GPIOs. Therefore, the hardware considerations necessary for the signal are the same as that of the GPIOs.
Page 208: Block Diagram
The switching frequency of HZ_CLK is 1.0 Hz. Therefore, layout and routing considerations are far less stringent as for other GPIOs and are somewhat relaxed. However, for best results, adhere to all GPIO layout recommendations. §§ ® 21-2 Intel PXA27x Processor Family Design Guide...
Page 209: Os Timer Interface
OS Timer Interface ® This chapter describes procedures for interfacing the OS Timer controller to Intel PXA27x Processor Family (PXA27x processor). 22.1 Overview The operating system timers block provides a set of timer channels that allow software to generate timed interrupts (or wakeup events). In the PXA27x processor, these interrupts are generated by two sets of timer channels: •...
Page 210: Channel Access/Control Block
OS Match Control Registers (OMCR4 - OMCR11) and generating the appropriate clocks and control signals for each timer channel. 22.3.2 PXA25x Compatibility Channels 0-3 Block ® This block maintains the four Intel PXA25x processor-compatible timer channels and for generating the appropriate channel-match signals. ® II:22-2...
Page 211: Channels 4 - 11 Blocks
OMCRx[CRES] bitfield, the signal must remained asserted for three clock periods of the source clock. ® ® Refer to Intel PXA270 Processor Electrical, Mechanical, and Thermal Specifications and Intel PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for all AC timing information. §§ ®...
Page 212 OS Timer Interface ® II:22-4 Intel PXA27x Processor Family Design Guide...
Page 213: Pulse-Width Modulator Interface
Signals The PWM signals are implemented through the GPIOs of the PXA27x processor. Refer to GPIO ® alternate function table in the GPIO chapter of the Intel PXA27x Processor Developers Manual for the GPIO assignments of the PWM signals. Table 23-1 for the list of signals controlled by the PWM controller of the PXA27x processor.
Page 214: Block Diagram
To ensure the noise is not induced into the contrast control or the processor, follow all recommendations for shielding the inverter and separating the inverter as far as possible from the contrast control line (PWM output.) §§ ® II:23-2 Intel PXA27x Processor Family Design Guide...
Page 215: General Purpose Input/Output Interfaces
PXA27x Processor Developers Manual for possible alternate function assignments. 24.2 Signals There are 119 GPIOs in discrete packages and 121 GPIOs in Intel® PXA27x Processor Family as ® described in GPIO table in the GPIO chapter of the Intel PXA27x Processor Developers Manual.
Page 216 GPIO reset signals. If the particular system implementation uses this function, the GPIOs must be ® designed such that this does not cause conflicts on the GPIOs. Refer to Section 3 of the Intel PXA27x Processor Developers Manual for information regarding this function.
Page 217: Block Diagram/Schematic
GPIOs. When configured with an alternate function, the maximum switching speed exceeds ® 10 MHz, depending upon the alternate function in use. Refer to the appropriate section in the Intel PXA27x Processor Developers Manual for more information on the maximum switching speed for GPIOs when configured with an alternate function.
Page 218 General Purpose Input/Output Interfaces ® II:24-4 Intel PXA27x Processor Family Design Guide...
Page 219: Interrupt Interface
Interrupt Interface ® This chapter describes the procedures for interfacing with the interrupt controller of Intel PXA27x Processor Family (PXA27x processor). 25.1 Overview The interrupt controller interfaces to both internal and external peripheral interrupt request. The means of interfacing an external peripheral interrupt request is through the GPIO signals. All the GPIO signals are configured to generate an interrupt on a rising edge, falling edge or both edges.
Page 220: Signals
GPIO resets and are disabled when PSSR[RDH] is clear Causes an second-level interrupt GPIO<120:2> Input/Output These signals cause an interrupt if an edge is detected and ICPR10 bit field is set. ® II:25-2 Intel PXA27x Processor Family Design Guide...
Page 221: Block Diagram
FIQ Interrupt to Register Processor Interrupt Source Interrupt Pending IRQ Interrupt to Register Processor IRQ Interrupt Pending Register FIQ Interrupt Pending Register Highest Priority Peripheral Priority Register Processor Interrupt Priority Register INT_001_P2 ® II:25-3 Intel PXA27x Processor Family Design Guide...
Page 222: Layout Notes
Induced noise as a result of an adjacent signal causes a spurious interrupt if amplitude of the adjacent signal is great enough and it meets the setup and hold timing requirements on both edges. §§ ® II:25-4 Intel PXA27x Processor Family Design Guide...
Page 223: Jtag Debug
JTAG Debug ® This chapter describes the boundary-scan (JTAG) features of Intel PXA27x Processor Family (PXA27x processor). The boundary-scan interface provides a means of driving and sampling the external pins of the processor, regardless of the state of the core. This function tests the processor’s electrical connections to the circuit board and (in conjunction with other devices on the circuit board having a similar interface) the integrity of the circuit board connections between devices.
Page 224: Features
In-system programming of programmable memory and logic devices on the PCB Refer to the IEEE 1149.1 standard for an explanation of the terms used in this section and a complete description of the TAP-controller states. ® II:26-2 Intel PXA27x Processor Family Design Guide...
Page 225: Signal Descriptions
For JTAG TAP operation, the nBATT_FAULT and nVCC_FAULT pins must always be driven high (de-asserted). An active low signal on either pin puts the device into sleep mode, which powers down all JTAG circuitry. ® II:26-3 Intel PXA27x Processor Family Design Guide...
Page 226: Pull-Up Resistors
3 This is a scan chain around the whole of the PXA27x. The scan chain allows the PXA27x core to be exercised (INTEST) and allows inter-device testing at a board level (EXTEST). The order of the scan chain is to be determined. ® II:26-4 Intel PXA27x Processor Family Design Guide...
Page 227: Jtag Instruction Register And Instruction Set
Table 26-2. The processor does not support the IEEE 1149.1 optional public instructions runbist, intest, and usercode. See Table 26-3 for description of the supported instructions in detail. ® II:26-5 Intel PXA27x Processor Family Design Guide...
Page 228 0b000_0010 Refer to Chapter 26, “Software Debug,” in the Intel PXA27x Processor Family Developers Manual . The clamp instruction allows the states of the signals driven from the PXA27x processor pins to be determined from the boundary-scan register while the bypass register is selected as the serial path...
Page 229: Test Data Registers
Part II: Section 26.4.4.2 — Boundary-Scan Register Part II: Section 26.4.4.3 — Data-Specific Registers Part II: Section 26.4.4.4 — Flash Data Register ® Part II: Section 26.4.4.5 — Intel XScale Data Registers Part II: Section 26.5.1 — JTAG Device Identification (ID) Register 26.4.4.1...
Page 230: Boundary-Scan Register
Chapter 3, ® “Clocks and Power Manager Unit,” in the Intel PXA27x Processor Family Developers Manual for details of sleep and deep-sleep modes. Thus, nBATT_FAULT, nVCC_FAULT, and nRESET must be driven high (de-asserted) for any instruction that uses the boundary-scan register.
Page 231: Data-Specific Registers
Intel XScale Data Registers ® Intel XScale Technology data registers are not documented here. They are used in conjunction ® with the user-defined JTAG instructions that are described in the Intel XScale Core Developer’s Manual. ® II:26-9 Intel PXA27x Processor Family Design Guide...
Page 232: Test Access Port (Tap) Controller
Figure 26-3. TAP Controller State Diagram Test-Logic-Reset Select-DR-Scan Select-IR-Scan Run-Test/Idle Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR Pause-IR Exit2-IR Exit2-DR Update-IR Update-DR NOTE: All state transitions are based on the value of TMS. ® II:26-10 Intel PXA27x Processor Family Design Guide...
Page 233: Test-Logic-Reset State
If TMS is high on the rising edge of TCK, the controller enters the Exit1-DR state. If TMS is low on the rising edge of TCK, the controller remains in the Shift-DR state. ® II:26-11 Intel PXA27x Processor Family Design Guide...
Page 234: Exit1-Dr State
When the TAP controller is in this state and TMS is held high on the rising edge of TCK, the controller enters the Select-DR-Scan state. If TMS is held low on the rising edge of TCK, the controller enters the Run-Test/Idle state. ® II:26-12 Intel PXA27x Processor Family Design Guide...
Page 235: Select-Ir-Scan State
The controller remains in this state as long as TMS is held low. When TMS goes high on the rising edges of TCK, the controller moves to the Exit2-IR state. ® II:26-13 Intel PXA27x Processor Family Design Guide...
Page 236: Exit2-Ir State
If TMS is held high on the rising edge of TCK, the controller enters the Select-DR-Scan state. If TMS is held low on the rising edge of TCK, the controller enters the Run-Test/Idle state. ® II:26-14 Intel PXA27x Processor Family Design Guide...
Page 237: Register Descriptions
Part Number 0b1001_0010_0110_0101 (0x9265) The JEDEC code is the manufacturer identification number: 11:0 JEDEC Code 0b0000_0001_0011 (0x013) † These values reflect the actual production identification and revision numbers embedded in the PXA27x processor. ® II:26-15 Intel PXA27x Processor Family Design Guide...
Page 238: Jtag Test Data Registers
JTAG test registers. 26.5.3 Debug Registers ® Refer to Chapter 26, “Software Debug,” of the Intel PXA27x Processor Family Developers Manual for detailed descriptions of the debug registers accessible through co-processor instructions. 26.6 Test Register Summary...
Page 239: Intel® Quick Capture Technology
Intel® Quick Capture Technology ® Intel Quick Capture Technology This chapter describes the guidelines for connecting camera image sensors and sensor modules to ® the Intel PXA27x processor’s quick capture interface. The PXA27x processor supports a wide variety of operating modes, data widths, formats, and clocking schemes. Only a subset of these modes are described in this chapter.
Page 240: Feature List
Intel® Quick Capture Technology 27.2 Feature List The functions of the quick capture interface: • Acquiring both data and control signals from a camera image sensor • Formatting of the data appropriately prior to being routed to memory through DMA The features of the quick capture interface include: •...
Page 241: Block Diagram
Intel® Quick Capture Technology 27.4 Block Diagram Figure 27-1 for illustration of a typical 8-bit master parallel connection between the PXA27x processor and an image sensor module. It is important to note that master mode refers to the case where the sensor module drives the line and frame synchronization signals. Slave mode is the case where the PXA27x processor drives the line and frame synchronization signals.
Page 242 Intel® Quick Capture Technology Figure 27-2. Interface Options Summary Master Parallel (MP) or Master Serial (MS) Interface Mode 4S, 5S, 8P, 9P, 10P Data Bus CMOS PXA27x MCLK Sensor Processor PCLK Slave Parallel (SP) Interface Mode 8P, 9P, 10P Data Bus...
Page 243: Pxa27X Dvk Block Diagram
PXA27x DVK Block Diagram This chapter contains the DVK (formerly NBMMNS2BVS DVK and formerly NBMMNS3BVS ® DVK) block diagrams of Intel PXA27x Processor Family (PXA27x processor). ® Intel PXA27x Processor Family Design Guide...
Page 244 Asynch Connector Flash SD/MMC or Memory Stick Mainstone II Baseboard Camera Spkr Scroll Wheel Note: Camera is mux’d on top of SSP1, PWM1 & ← ↵ USIM Camera / LCD Module Key Board ® Intel PXA27x Processor Family Design Guide...
Page 245 20MHz Switch Power subsystem Main_1.8V 2.5V (FPGA/CPLD core) Main_3.15V Main_5V (PCMCIA) for asserting App Processor RJ45 VDD/BATT_FLT EEPROM SIM 1.8/3V Wall Supply Jack Silent Alert Header for EEPROM control Test Quest Switch Pads ® Intel PXA27x Processor Family Design Guide...
Page 246 In/Out Expansion Connector iRDA mic spk. Hand Head Asynchronous Flash MAIN BOARD I2C Header SSP Header LCD Connector COMPONENTS Notes: * This device interfaces can be muxed (to communication processor or application processor). ® Intel PXA27x Processor Family Design Guide...
Page 247 PXA27x DVK Block Diagram Figure A-4. Liquid Crystal Display Block Diagram LCD Config Register (RO) L_DD Backlight/Frontlight PWM0 Touch Screen TSxy ® Intel PXA27x Processor Family Design Guide...
Page 248 Figure A-5. Audio Module Block Diagram Mainstone II Daughter Card Communication PXA27x AD6521 AD6521 Processor Processor Garson Mainstone Baseboard Bluetooth Header Bluetooth SSP SSP2 Audio CODEC Board Touchscreen Digitizer Line Line Microphone Line Out Line Out ® Intel PXA27x Processor Family Design Guide...
Page 249 ↵ caps Record Flip MK_OUT7 space Speaker Scroll Wheel DK_IN0, DK_IN1, DK_IN2 with "press" L_DD / PWM0 / TSxy Keypad / LCD / Backlight / Camera / Mic / Touch Connector Spkr Connector ® Intel PXA27x Processor Family Design Guide...
Page 250 CPLD1 is seen on the JTAG chain Auxiliary JTAG DSP Comms Test pads JTAG Stake pins JTAG Stake Pins CPLD2 EEPROM PCMCIA glue FPGA Xcvr control 1.8V / 3.3V IO Platform Registers 5V tolerant nCS2L §§ ® Intel PXA27x Processor Family Design Guide...
Page 251: Pxa27X Processor Developer's Kit (Dvk)
® Intel NBMMNS2BVS DVK for Intel Personal Internet Client Architecture Quick Start Guide Intel Power Manager for NBMMNS2BVS DVK and NBMMNS2BVGS DVK Application Note ® Intel Diagnostics for NBMMNS2BVS DVK for Intel Personal Internet Client Architecture User's Guide Upgrading Processor Cards for NBMMNS2BVS DVK and NBMMNS2BVGS DVK Quick Start Guide ®...
Page 252 PXA27x Processor Developer’s Kit Parts List ® Intel PXA27x Processor Developer’s Kit Quick Start Guide ® Board Bring Up (BBU) Program for the Intel PXA270 Processor Developer’s Kit Release Notes ® Board Bring Up (BBU) Program for the Intel PXA27x Processor MultiChip Product Developer’s Kit Release Notes ®...
Page 253: Pxa27X Dvk Bill-Of-Materials
PXA27x DVK Bill-of-Materials ® For the Bills of Materials (BOM) that correspond to the current revision of Intel PXA27x Processor Family (PXA27x processor) DVK, refer to Appendix B , “PXA27x Processor Developer’s Kit (DVK).” To locate a specific parts list, refer to the appropriate tables in Appendix B: ®...
Page 254 PXA27x DVK Bill-of-Materials ® Intel PXA27x Processor Family Design Guide...
Page 255: Intel Pxa27X Processor And Intel Pxa25X Processor Differences
Intel PXA27x Processor and Intel PXA25x Processor Differences Introduction ® This appendix describes the changes and enhancements found in the Intel PXA27x Processor ® Family (PXA27x processor) compared to the Intel PXA25x processor. The differences are explained separately for each peripheral.
Page 256 The internal memory controller has been added to the PXA27x processor. This controller does not exist in the PXA25x processor. The features of the internal memory controller are listed in the ® internal memory chapter of the Intel PXA27x Processor Family Developers Manual. ®...
Page 257 ® ® Intel PXA27x Processor and Intel PXA25x Processor Differences DMA Controller The DMA controllers in the PXA27x processor and PXA25x processor are similar with these exceptions: • Features added to the DMA controller of the PXA27x processor: — Additional 16 DMA channels for a total of 32 DMA channels —...
Page 258 ® ® Intel PXA27x Processor and Intel PXA25x Processor Differences Memory Controller The memory controllers in the PXA27x processor and PXA25x processor are similar with the following exceptions. • Features added to the PXA27x processor memory controller: — Support for low power SDRAM includes: ◆...
Page 259 ® ® Intel PXA27x Processor and Intel PXA25x Processor Differences LCD Controller The LCD controllers in the PXA27x processor and PXA25x processor are similar with these exceptions: • Features added to the PXA27x processor memory controller: — Support for these Display modes: ◆...
Page 260 ® ® Intel PXA27x Processor and Intel PXA25x Processor Differences — TCR register has an additional field to enhance TMED support. — FDADR1-FDADR6 registers added to support new overlays and cursor. — FBR1-FBR6 registers added to support new overlays and cursor.
Page 261 When used outside of the voltage change sequencer, there are no restrictions to the use of the I ® — When the Voltage Change Sequencer is operating, (see Section 3.5.1.14 of the Intel PXA27x Processor Family Developers Manual), the PWR_I C registers are not writable and reads unknown values.
Page 262 ® ® Intel PXA27x Processor and Intel PXA25x Processor Differences D.11 Fast Infrared Communication Port The FIR controllers in the PXA27x processor and PXA25x processor are similar with these exceptions: • The FICP in PXA27x processor is selected to use all 32 bits of the Peripheral Bus.
Page 263 ® ® Intel PXA27x Processor and Intel PXA25x Processor Differences D.13 AC ‘97 The AC ‘97 controllers in the PXA27x processor and PXA25x processor are similar with the exception of these features: • An optional output AC97_SYSCLK (approximately 24.5 MHz) clock signal is available on the PXA27x processor.
Page 264 The keypad controller has been added to the PXA27x processor. This controller does not exist in the PXA25x processor. ® The features of the keypad controller are listed in the Keypad Interface chapter of the Intel PXA27x Processor Family Developers Manual. D.19 Universal Subscriber ID Interface The Universal Subscriber ID Interface has been added to the PXA27x processor.
Page 265 ® ® Intel PXA27x Processor and Intel PXA25x Processor Differences D.21 Real-Time Clock (RTC) The real-time clock (RTC) controller of the PXA27x processor is similar to that of the PXA25x processor except for these changes: • Features added to the PXA27x processor real time clock: —...
Page 266 ® ® Intel PXA27x Processor and Intel PXA25x Processor Differences D.22 Operating System Timers The Operating System timers in the PXA27x processor and PXA25x processor are similar with these exceptions: • Features added to the PXA27x processor operating system timers: —...
Page 267 ® ® Intel PXA27x Processor and Intel PXA25x Processor Differences D.23 Pulse-Width Modulator Controller The PWM controllers in the PXA27x processor and PXA25x processor are similar with these exceptions: • Features added to the PWM controller of the PXA27x processor: —...
Page 268 • Features added to the PXA27x processor GPIO controller: — There are now 119 GPIOs in discrete packages and 121 GPIOs in Intel® PXA27x Processor Family, whereas in the PXA25x processor, there are 81 GPIOs. — Some alternate functions of the PXA27x processor have signals that are bidirectional.
Page 269 ® ® Intel PXA27x Processor and Intel PXA25x Processor Differences D.26 Debug/Test This subsection describes separate changes to the software debug module and the hardware TAP controller (also referred to as the Test Interface from the PXA25x processor). D.26.1 Software Debug Module There were no changes to the software debug module.
Page 270 ® ® Intel PXA27x Processor and Intel PXA25x Processor Differences ® D-16 Intel PXA27x Processor Family Design Guide...
Page 271: Companion Components For Pxa27X Processor
Processor Electrical, Mechanical and Thermal Specification and Intel PXA27x Processor Family Electrical, Mechanical, and Thermal Specification for the PXA27x processor, whether they are from this list, contained in the Bill of Materials (BOM) for either Intel reference platforms or Intel development platforms. System Architecture...
Page 272 Austria MIcrosystems Dialog Semiconductor Empirion Epson International Rectifier Intersil Linear Technologies Maxim Micrel National Semiconductor ON Semiconductor Panasonic Philips RichTek Rohm SemTech Board Vendors Accelent Applied Data Systems Fairchild Sophia Systems Stellcom Internal Memory ® Intel PXA27x Processor Family Design Guide...
Page 273 C Bus Interface Unit E.10 UARTs E.11 Fast Infrared Communication Port E.12 USB Device (OTG) Controller This section describes the transceivers needed for USB OTG support determined to be compatible with the PXA27x processor. ® Intel PXA27x Processor Family Design Guide...
Page 274 VBAT power supply: 3.0 to 3.6 V for USB ports and digital logic VDD_LDG power supply: 1.65 to 3.6V for low power digital I/O interface Built-in ESD protection Available in small (4x4 mm2) HVQFN24 package ® Intel PXA27x Processor Family Design Guide...
Page 275 Companion Components for PXA27x Processor E.13 AC ‘97 E.14 S (Inter IC Sound Controller) E.15 MultiMediaCard/SD/SDIO Controller E.16 Intel(R) Mobile Scalable Link E.17 Memory Stick Host Controller E.18 Keypad Interface E.19 Universal Subscriber ID Interface E.20 Universal Serial Bus Host Controller E.21...
Page 276 Companion Components for PXA27x Processor ® Intel PXA27x Processor Family Design Guide...
Page 277: Glossary
Bandwidth. The amount of data transmitted per unit of time, typically bits per second (bps) or bytes per second (Bps). The size of a network “pipe” or channel for communications in wired networks. In wireless, it refers to the range of available frequencies that carry a signal. ® Glossary-1 Intel PXA27x Processor Family Design Guide...
Page 278 CDMA (Code Division Multiple Access). U.S. wireless carriers Sprint PCD and Verizon use CDMA to allocate bandwidth for users of digital wireless devices. CDMA distinguishes between multiple transmissions carried simultaneously on a single wireless signal. It carries the transmissions on that signal, freeing network room for the ® Glossary-2 Intel PXA27x Processor Family Design Guide...
Page 279 The result of a CRC is typically stored or transmitted with the checked data. The stored or transmitted result is compared to a CRC calculated for the data to determine if an error has occurred. ® Intel PXA27x Processor Family Design Guide Glossary-3...
Page 280 Digital Volt Meter. This equipment is used for measuring voltage across a series resistor, preferable for high current power supplies. For low power supplies, the voltage drop is too small for detection by the DVM. ® Glossary-4 Intel PXA27x Processor Family Design Guide...
Page 281 False EOP. A spurious, usually noise-induced event that is interpreted by a packet receiver as an EOP. FDD. The Mobile Station transmits on one frequency; the Base Station transmits on another frequency FDM. Frequency Division Multiplexing. Each Mobile station transmits on a different frequency (within a cell). ® Intel PXA27x Processor Family Design Guide Glossary-5...
Page 282 GPRS wireless devices are “always on” in that they can send and receive data without dial-ins. GPRS works with GSM. GPS. Global Positioning System allows location of an object anywhere on earth using a constellation of satellites orbiting the earth. GPIO. General Purpose Inputs/Outputs ® Glossary-6 Intel PXA27x Processor Family Design Guide...
Page 283 Hub Tier. One plus the number of USB links in a communication path between the host and a function. IMMU. Instruction Memory Management Unit, part of the Intel® XScale™ core. I-Mode. A Japanese wireless service for transferring packet-based data to handheld devices created by NTT DoCoMo.
Page 284 Transmission rate expressed in kilobits per second. A measurement of bandwidth in the U.S. kBps. Transmission rate expressed in kilobytes per second. KPC. Keypad Interface Control LCD. Liquid Crystal Display ® Glossary-8 Intel PXA27x Processor Family Design Guide...
Page 285 MMC. Multimedia Card. Small form factor memory and I/O card MMX Technology. The Intel® MMX™ technology comprises a set of instructions that are designed to greatly enhance the performance of advanced media and communications applications. Refer to Chapter 10 of the Intel Architecture Software Developers Manual, Volume 3: System Programming Guide, Order #245472.
Page 286 A pipe has several attributes; for example, a pipe may transfer data as streams (stream pipe) or messages (message pipe). See also Stream Pipe and Message Pipe. PLL. See Phase Locked Loop. PM. Phase Modulation ® Glossary-10 Intel PXA27x Processor Family Design Guide...
Page 287 Root Hub. A USB hub directly attached to the Host controller. This hub (tier 1) is attached to the host. Root Port. The downstream port on a Root Hub. RTC. Real-Time Clock ® Intel PXA27x Processor Family Design Guide Glossary-11...
Page 288 SA-1110. StrongARM* based applications processor for handheld products ® Intel StrongARM* SA-1111. Companion chip for the Intel® SA-1110 processor SAD. Sum of absolute differences Sample. The smallest unit of data on which an endpoint operates; a property of an endpoint.
Page 289 SRAM. Static Random Access Memory SRC. See Sample Rate Conversion. SSE. Streaming SIMD Extensions SSE2. Streaming SIMD Extensions 2: for Intel Architecture machines, 144 new instructions, a 128-bit SIMD integer arithmetic and 128-bit SIMD double precision floating point instructions, enabling enhanced multimedia experiences.
Page 290 Transfer. One or more bus transactions to move information between a software client and its function. Transfer Type. Determines the characteristics of the data flow between a software client and its function. Four standard transfer types are defined: control, interrupt, bulk, and isochronous. TS. Thermal Shock ® Glossary-14 Intel PXA27x Processor Family Design Guide...
Page 291 Internet content, check voice mail and e-mail, receive text of faxes and conduct transactions. WAP works with multiple standards, including CDMA and GSM. Not all mobile devices support WAP. ® Intel PXA27x Processor Family Design Guide Glossary-15...
Page 292 Word. A data element that is four bytes (32 bits) in size. WML. Wireless Markup Language. A version of HDML based on XML. Wireless applications developers use WML to re-target content for wireless devices. §§ ® Glossary-16 Intel PXA27x Processor Family Design Guide...
Page 293: Index
Example Power Supply Utilizing Minimal Regulators I:4-2 Bluetooth UART II:10-5 Exit1 Block Diagram II:10-5 DR State II:26-12 Signals II:10-5 IR State II:26-13 Boundary-Scan Register II:26-8 Bus Host Controller, Universal Serial II:D-10 Exit2 ® IX-1 Intel PXA27x Processor Family Design Guide...
Page 294 Index DR State II:26-12 Instructions IR State II:26-14 TRISTATE II:26-6 External 13.00-MHz Clock II:3-8 Intel XScale® Data Registers II:26-9 External 32.768-KHz Clock II:3-7 Intel(R) Mobile Scalable Link External Clock Enable Configuration Scheme II:E-5 ® II:8-5 Intel Flash Memory Design Guidelines I:2-1 ®...
Page 295: Overview......................................................................................................................ii:
GPIOn and GPIOx are Same Pin II:12-4 Preconditioning and Moisture Sensitivity I:2-11 OS Timer Interface II:22-1 Pull-Up Resistors II:26-4 OTG ID II:12-11 Pull-Ups and Pull-Downs II:9-4 Other Uses of I2C II:9-3 Pulse-Width Modulator Controller Output Control II:22-3 ® Intel PXA27x Processor Family Design Guide IX-3...
Page 296: Signals .........................................................................................................................Ii:
Shift-DR State II:26-11 Test Data Registers II:26-7 Shift-IR State II:26-13 Test Interface Signal Descriptions II:26-3 II:D-15 Signal Pin Descriptions I:1-3 Test Register Summary II:26-16 Signal Routing and Buffering II:7-4 Test-Logic-Reset State II:26-11 Signals II:11-1 ® IX-4 Intel PXA27x Processor Family Design Guide...
Page 297: Signals ............................................................................................Ii:
USB On-The-Go Transceivers II:E-4 USB On-The-Go Transceivers II:E-4 USIM Card Interface Signals II:19-3 Controller Interface II:19-1 Variable Latency Input/Output Interface II:6-22 VLIO Block Diagram II:6-24 Memory Layout Notes II:6-24 Memory Signals II:6-23 §§ ® Intel PXA27x Processor Family Design Guide IX-5...

Intel PXA27 Series Design Manual

Table of Contents

Table of Contents

Part I

PCB Design Guidelines

Design Check List

Mixed Voltage Design Considerations

Power Measurements

Introduction to Part II

Package and Pins

Tables

Part II

Clocks and Power Interface

Internal SRAM

DMA Controller Interface

System Memory Interface

LCD Interface

SSP Port Interface

UART Interfaces

Fast Infrared Interface

USB Client Controller

I2S Interface

Multimediacard/Sd/Sdio Card Controller

Baseband Interface

Memory Stick Host Interface

Keypad Interface

USIM Controller Interface

Universal Serial Bus Host Interface

Real Time Clock Interface

OS Timer Interface

Pulse-Width Modulator Interface

General Purpose Input/Output Interfaces

Interrupt Interface

JTAG Debug

Intel® Quick Capture Technology

Appendix

Pxa27X DVK Block Diagram

Pxa27X Processor Developer's Kit (DVK)

Pxa27X DVK Bill-Of-Materials

Intel Pxa27X Processor and Intel Pxa25X Processor Differences

Companion Components for Pxa27X Processor

Glossary

Index

Quick Links

Chapters

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Questions and answers

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Summary of Contents for Intel PXA27 Series