Gpdr0 Bit Definitions; Gpdr1 Bit Definitions; Gpdr2 Bit Definitions - Intel PXA255 Developer's Manual

Table 4-6. GPDR0 Bit Definitions
Physical Address
0x40E0_000C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
Bits Name
<31:0> PD[x]
Table 4-7. GPDR1 Bit Definitions
Physical Address
0x40E0_0010
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
Bits Name
<31:0> PD[x]
Table 4-8. GPDR2 Bit Definitions
Physical Address
0x40E0_0014
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reserved
Reset 0 0 0 0 0 0
Bits Name
<31:21>
<20:0> PD[x]
4.1.3.3 GPIO Pin Output Set Registers (GPSR0, GPSR1, and GPSR2) and Pin
Output Clear Registers (GPCR0, GPCR1, GPCR2)
Intel® PXA255 Processor Developer's Manual
0 0 0 0 0 0 0
GPIO Pin 'x' Direction (where x = 0 to 31).
0 – Pin configured as an input
1 – Pin configured as an output
0 0 0 0 0 0 0
GPIO Pin 'x' Direction (where x = 32 to 63).
0 – Pin configured as an input.
1 – Pin configured as an output.
0 0 0 0 0 0 0
— reserved
GPIO Pin 'x' Direction (where x = 64 to 84).
0 – Pin configured as an input.
1 – Pin configured as an output
GPDR0
0 0 0 0 0 0 0 0
Description
GPDR1
0 0 0 0 0 0 0 0
Description
GPDR2
0 0 0 0 0 0 0 0
Description
System Integration Unit
System Integration Unit
8 7 6 5 4 3
0 0 0 0 0 0 0 0
System Integration Unit
8 7 6 5 4 3
0 0 0 0 0 0 0 0
System Integration Unit
8 7 6 5 4 3
0 0 0 0 0 0 0 0
2 1 0
0 0 0
2 1 0
0 0 0
2 1 0
0 0 0
4-9