Pin Mapping To Sdram Devices With Normal Bank Addressing - Intel PXA255 Developer's Manual

Intel computer hardware user manual

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Table 6-8. External to Internal Address Mapping for SA-1111 Addressing (Sheet 3 of 3)

External Address pins at SDRAM RAS Time

24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

2x13x8x32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

NOT VALID (illegal addressing combination)

2x13x9x32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

2x13x9x16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

2x13x10x16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Use the information below to connect the processor to the SDRAM devices. Some of the

addressing combinations may not apply in SA1111 addressing mode. See

listing of supported addressing combinations and how to connect the PXA255 processor to the

Table 6-9. Pin Mapping to SDRAM Devices with Normal Bank Addressing (Sheet 1 of 3)

MA24 MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10

Intel® PXA255 Processor Developer's Manual

NOT VALID (too big)

Pin mapping to SDRAM devices for Normal Addressing.

MA[24:10] represent the address signals driven from the processor.

NOT VALID (illegal addressing combination)

External Address pins at SDRAM CAS Time

NOT VALID (illegal addressing combination)

NOT VALID (too big)

NOT VALID (too big)

Memory Controller

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