Isr Bit Definitions - Intel PXA255 Developer's Manual

2
I C Bus Interface Unit
Table 9-11. ISR Bit Definitions (Sheet 1 of 2)
Physical Address
4030_1698
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reset 0 0 0 0 0 0
31:11
10
9
8 GCAD
7
6
5
4
3
2
9-26
2
I C Status Register
reserved
0 0 0 0 0 0 0
— reserved
Bus Error Detected:
0 = No error detected.
2
1 = The I C unit sets this bit when it detects one of the following error conditions:
• As a master transmitter, no ACK is detected on the interface after a byte is sent.
BED
• As a slave receiver, the I
NOTE:When an error occurs, I
misplaced START and STOP conditions do not occur. See
To clear this bit, write a 1 to it.
Slave Address Detected:
0 = No slave address detected.
2
SAD 1 = I C unit detected a 7-bit address that matches the general call address or ISAR. An
interrupt is signalled when the SADIE interrupt is set to a 1.
To clear this bit, write a 1 to it.
General Call Address Detected:
0 = No general call address received.
2
1 = I C unit received a general call address.
IDBR Receive Full:
0 = The IDBR has not received a new data byte or the I
IRF 1 = The IDBR register received a new data byte from the I
when the IRFIE is set to a 1.
To clear this bit, write a 1 to it.
IDBR Transmit Empty:
0 = The data byte is still being transmitted.
2
ITE 1 = The I C unit has finished transmitting a data byte on the I
signalled when the ITEIE interrupt is set to 1.
To clear this bit, write a 1 to it.
Arbitration Loss Detected: used during multi-master operation.
0 = Cleared when arbitration is won or never took place.
ALD
1 = Set when the I
To clear this bit, write a 1 to it.
Slave STOP Detected:
0 = No STOP detected.
SSD
1 = Set when the I
To clear this bit, write a 1 to it.
2
I C Bus Busy:
IBB 2
0 = I C bus is idle or the I
1 = Set when the I
Unit Busy:
UB 2
0 = I C unit not busy.
1 = Set when the I
0 0 0 0 0 0 0 0
2
C unit generates a NAK pulse.
2
C bus transactions continue. Software must ensure that
2
C unit loses arbitration.
2
C unit detects a STOP while in slave-receive or slave-transmit mode.
2
C unit is using the bus (i.e., unit busy).
2 2
C bus is busy but the I C unit is not involved in the transaction.
2
C unit is busy. Defined as the time between the first START and STOP.
Intel® PXA255 Processor Developer's Manual
2
I C Bus Interface Unit
8 7 6 5 4 3
0 0 0 0 0 0 0 0
Section 9.4.5.
2
C unit is idle.
2
C bus. An interrupt is signalled
2
C bus. An interrupt is
2 1 0
0 0 0