Intel Agilex Configuration Details; Intel Agilex Configuration Timing Diagram - Intel Agilex Series Configuration User Manual

683673 | 2021.10.29
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2. Intel Agilex Configuration Details

2.1. Intel Agilex Configuration Timing Diagram

Figure 4. Power-On, Configuration, and Reconfiguration Timing Diagram
nCONFIG
nSTATUS
(weak int/ext pullup)
CONF_DONE
INIT_DONE
nINIT_DONE
(internal signal)
MSEL[2:0]
Data[<n>-1:0](Generic)
AVST_READY (Avalon ST only)
AVST_VALID (Avalon ST only)
AS_CS0 (AS only)
Configuration_State
Power_Supply_Status[7:0]
GPIO Status
Note:
(1) All I/O pins in SDM and HPS bank except the VSIGP_0, VSIGN_0, VSIGP_1, VSIGN_1, and RREF_SDM pins are in undetermined state during device power up and power down.
Input signals of an I/O pin at any point during the power up and power down should not exceed the I/O buffer power supply rail of the bank. When using pin in the GPIO bank with 1.5V VCCIO_PIO, the pin voltage must
not exceed the VCCIO_PIO rail or 1.2V, whichever is lower.
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Power-On Reset
3
(1)
(1)
(1)
(1)
(1)
1
Sample
(1)
(1)
...
(1)
...
(1)
...
...
(1)
2
Power On SDM Start Idle
Configuration
Group 1 Group 2 Group 3
Supply Up Supply Up Supply Up
(1)
Tri-Stated with Weak Pull-Up
Reconfiguration Triggered
Reconfiguration
1
4
User Mode
5
2
User Mode Device Clean
Initialization
User Defined
4
3 5
...
...
...
...
Idle Configuration Initialization
Tri-Stated with Weak Pull-Up
User Mode
User Defined
ISO
9001:2015
Registered