Single Block Read - Intel PXA255 Developer's Manual

•
Update the MMC_CMDAT register as:
— Write 0x01 to MMC_CMDAT[RESPONSE_FORMAT]
— Set the MMC_CMDAT[DATA_EN] bit.
— Set the MMC_CMDAT[WRITE/READ] bit.
— Clear the MMC_CMDAT[STREAM_BLOCK] bit.
— Clear the MMC_CMDAT[BUSY] bit.
— Clear the MMC_CMDAT[INIT] bit.
•
Turn the clock on.
After it starts the clock, the software must perform these steps:
1. Wait for the response as described in
2. Write data to the MMC_TXFIFO FIFO and continue until all of the data has been written to
the FIFO.
Note: If a piece of data smaller than 32 bytes is written to the FIFO, the MMC_PRTBUF register must be
set.
3. Set MMC_I_MASK register to 0x1e and wait for MMC_I_REG[DATA_TRAN_DONE]
interrupt.
4. Set MMC_I_MASK to 0x1d.
5. Wait for MMC_I_REG[PRG_DONE] interrupt. This interrupt indicates that the card has
finished programming. Software may wait for MMC_I_REG[PRG_DONE] or start another
command sequence on a different card.
6. Read the MMC_STAT register to verify the status of the transaction (i.e. CRC error status).
To address a different card, the software sends a select command to that card by sending a basic no
data command and response transaction. To address the same card, the software must wait for
MMC_I_REG[PRG_DONE] interrupt. This ensures that the card is not in the busy state.
15.4.7

Single Block Read

In a single block read command, the software must stop the clock and set the registers as described
in Section
Intel® PXA255 Processor Developer's Manual
15.4.4.
Section 15.4.4.
MultiMediaCard Controller
15-19