Multiple Interrupts - Renesas R8C/Tiny Series Software Manual

Chapter 5 Interrupts

5.6 Multiple Interrupts

The internal bit states when control has branched to an interrupt routine are as follows:
• The interrupt enable flag (I flag) is cleared to 0 (interrupts disabled).
• The interrupt request bit for the acknowledged interrupt is cleared to 0.
• The processor interrupt priority level (IPL) equals the interrupt priority level of the acknowledged interrupt.
By setting the interrupt enable flag (I flag) to 1 in the interrupt routine, interrupts can be reenabled so that an
interrupt request that has higher priority than the processor interrupt priority level (IPL) can be acknowl-
edged. Figure 5.6.1 shows how multiple interrupts are handled.
Interrupt requests that have not been acknowledged due to low interrupt priority level are kept pending.
When the IPL is restored by an REIT instruction and the interrupt priority is determined based on the IPL
contents, the pending interrupt request is acknowledged if the following condition is met:
Interrupt priority level of
pending interrupt request
Rev.2.00 Oct 17, 2005
REJ09B0001-0200
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Restored processor interrupt
priority level (IPL)
5.6 Multiple interrupts