Table of Contents
Advertisement
Section 21 FSI Interface
21.3.2
FSI Control Register 2 (FSICR2)
The FSICR2 control bits are classified into two functionalities: enabling/disabling the FSI
communications and enabling/disabling the FSI internal interrupts.
Bit
Bit Name
7
TE
6
RE
5
FSITEIE
4
FSIRXIE
3 to 0
Rev. 1.00 Apr. 28, 2008 Page 688 of 994
REJ09B0452-0100
R/W
Initial
Value
EC
Host Description
0
R/W
0
R/W
0
R/W
0
R/W
All 0
R/W
FSI Transmit Enable
Controls FSI transmission and indicates transmission
status in combination with the LFBUSY bit.
0: FSI transmission wait state
[Clearing condition]
When FSI data transmission is completed.
1: When LFBUSY = 0: Starts transmission.
When LFBUSY = 1: FSI transmission is in progress
(automatically set).
FSI Reception Enable
Controls FSI reception and indicates reception status
in combination with the LFBUSY bit.
0: FSI reception wait state
[Clearing condition]
When FSI data reception is completed.
1: When LFBUSY = 0: Starts reception.
When LFBUSY = 1: FSI reception is in progress
(automatically set).
FSI Transmit End Interrupt Enable
0: Disables the FSITEI interrupt request.
1: Enables the FSITEI interrupt request.
FSI Receive Interrupt Enable
0: Disables the FSIRXI interrupt request.
1: Enables the FSIRXI interrupt request.
Reserved
The initial value should not be modified.
Advertisement
Table of Contents
