Register Descriptions - Renesas H8S/2100 Series Hardware Manual

2
Section 18 I C Bus Interface (IIC)
18.3

Register Descriptions

2
The I C bus interface has the following registers. Registers ICDR and SARX and registers ICMR
and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit
in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit
is set to 1, ICMR and ICDR can be accessed. For details on the serial timer control register, see
section 3.2.3, Serial Timer Control Register (STCR).
Table 18.2 Register Configuration
Channel Register Name
2
Channel 0 I C bus extended control register_0
2
I C bus control register_0
2
I C bus status register_0
2
I C bus data register_0
Second slave address register_0
2
I C bus mode register_0
Slave address register_0
2
I C bus control initialization
register_0
2
Channel 1 I C bus extended control register_1
2
I C bus control register_1
2
I C bus status register_1
2
I C bus data register_1
Second slave address register_1
2
I C bus mode register_1
Slave address register_1
Rev. 1.00 Apr. 28, 2008 Page 534 of 994
REJ09B0452-0100
Abbreviation R/W
ICXR_0 R/W H'00
ICCR_0 R/W H'01
ICSR_0 R/W H'00
R/W 
ICDR_0
SARX_0 R/W H'01
ICMR_0 R/W H'00
SAR_0 R/W H'00
ICRES_0 R/W H'0F
ICXR_1 R/W H'00
ICCR_1 R/W H'01
ICSR_1 R/W H'00
R/W 
ICDR_1
SARX_1 R/W H'01
ICMR_1 R/W H'00
SAR_1 R/W H'00
Initial Data Bus
Value Address Width
H'FED4 8
H'FFD8 8
H'FFD9 8
H'FFDE 8
H'FFDE 8
H'FFDF 8
H'FFDF 8
H'FEE6 8
H'FED5 8
H'FF88 8
H'FED0*
H'FF89 8
H'FED1*
H'FF8E 8
H'FECE*
H'FF8E 8
H'FECE*
H'FF8F 8
H'FECF*
H'FF8F 8
H'FECF*