Tcm Interrupt Enable Register (Tcmier) - Renesas H8S/2100 Series Hardware Manual

11.3.8

TCM Interrupt Enable Register (TCMIER)

TCMIER is an 8-bit readable/writable register that enables or disables interrupt requests.
Initial
Bit Bit Name Value
7 OVIE 0
6 MAXOVIE 0
5 CMIE 0
4 TCMIPE 0
3 ICPIE 0
R/W Description
R/W Counter Overflow Interrupt Enable
Enables or disables the issuing of interrupt requests on
setting of the OVF flag in TCMCSR to 1.
0: Disable interrupt requests by OVF
1: Enable interrupt requests by OVF
R/W Cycle Upper Limit Overflow Interrupt Enable
Enables or disables the issuing of interrupt requests on
setting of the MAXOVF flag in TCMCSR to 1.
0: Disable interrupt requests by MAXOVF
1: Enable interrupt requests by MAXOVF
R/W Compare Match Interrupt Enable
Enables or disables the issuing of interrupt requests when
the CMF bit in TCMCSR is set to 1.
0: Disable interrupt requests by CMF
1: Enable interrupt requests by CMF
R/W Input Capture Input Enable
Enables or disables input to the pin. When using interrupt
capture mode and cycle measurement mode, set this bit to
1.
0: Disable input
1: Enable input
Note: Modify this bit when CST = 0 and TCMMDS = 0.
R/W Input Capture Interrupt Enable
Enables or disables interrupt requests when the ICPF flag in
TCMCSR is set to 1.
0: Disable interrupt requests by ICPF
1: Enable interrupt requests by ICPF
Section 11 16-Bit Cycle Measurement Timer (TCM)
Rev. 1.00 Apr. 28, 2008 Page 315 of 994
REJ09B0452-0100