Kbf Setting Timing And Kclk Control - Renesas H8S/2100 Series Hardware Manual

16-bit single-chip microcomputer

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Section 19 Keyboard Buffer Control Unit (PS2)

KBF Setting Timing and KCLK Control

Figure 19.11 shows the KBF setting timing and the KCLK pin states.

Falling edge

Note: * φ here indicates the clock signal frequency-divided by N for medium-speed mode.

Figure 19.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing

Rev. 1.00 Apr. 28, 2008 Page 606 of 994

REJ09B0452-0100

Automatic I/O inhibit

H8s/2117r series R4f2117r