Cycle Measurement Mode - Renesas H8S/2100 Series Hardware Manual

(3) CMF Setting Timing when a Compare Match Occurs
The CMF flag in TDPCSR is set in the last state in which the values in TDPCNT and TDPWDMX
match (timing when TDPCNT updates the matched count value) in timer mode. Accordingly, a
compare match signal is not generated until an additional cycle of the TDPCNT input clock is
generated after a match between the values in TDPCNT and TDPWDMX. For details, see section
12.6.2, Conflict between TDPPDMX Write and Compare Match. Figure 12.6 shows the timing on
which the CMF flag is set.
φ
TDPCNT
TDPWDMX
Compare match
signal
CMF
Figure 12.6 Timing of CMF Flag Setting on Compare Match
12.4.2

Cycle Measurement Mode

The TDP operates in cycle measurement mode when the TDPMDS bit in TDPCR1 is set to 1.
(1) Counter Operation
TDPCNT counts up in cycle measurement mode regardless of the setting of the CST bit in
TDPCR1. TDPCNT is cleared to H'0000 when the first edge in the measurement period is
detected, from which state it counts up. Figure 12.7 shows an example of counter operation in
cycle measurement mode.
φ
TDPCYI
TDPCNT
clear signal
TDPCNT
input clock
TDPCNT
Figure 12.7 Example of Counter Operation in Cycle Measurement Mode
N
N H'0000 H'0001
Section 12 16-Bit Duty Period Measurement Timer (TDP)
N + 1
N
H'0002
Rev. 1.00 Apr. 28, 2008 Page 345 of 994
H'0003 H'0000 H'0001
REJ09B0452-0100