Register Descriptions - Renesas H8S/2100 Series Hardware Manual

24.7

Register Descriptions

The flash memory has the following registers and parameters.
Table 24.3 Register Configuration
Register Name
Flash code control status register
Flash program code select register
Flash erase code select register
Flash key code register
Flash MAT select register
Flash transfer destination address
register
Note: Bits other than the SCO bit are read-only bits. The SCO bit is a write-only bit and is
*
always read as 0.
Table 24.4 Parameter Configuration
Register Name
Download path fail result parameter
Flash path/fail parameter
Flash program/erase frequency
parameter
Flash multipurpose address area
parameter
Flash multipurpose data destination
parameter
Flash erase block select parameter
Note: One byte of the start address on the on-chip RAM specified by FTDAR
*
Abbreviation R/W
FCCS R/W*
FPCS R/W
FECS R/W
FKEY R/W
FMATS R/W
FTDAR R/W
Abbreviation R/W
DPFR R/W*
FPFR R/W
FPEFEQ R/W
FMPAR R/W
FMPDR R/W
FEBS R/W
Section 24 Flash Memory
Initial
Value Address
H'80 H'FEA8
H'00 H'FEA9
H'00 H'FEAA
H'00 H'FEAC
H'00 H'FEAD
H'00 H'FEAE
Initial
Value Address
Undefined On-chip
RAM*
Undefined R0L of
CPU
Undefined ER0 of
CPU
Undefined ER1 of
CPU
Undefined ER0 of
CPU
Undefined ER0 of
CPU
Rev. 1.00 Apr. 28, 2008 Page 757 of 994
REJ09B0452-0100
Data Bus
Width
8
8
8
8
8
8
Data Bus
Width
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32