Timer Control Register (Tcr) - Renesas H8S/2100 Series Hardware Manual

Section 13 8-Bit Timer (TMR)
13.3.4

Timer Control Register (TCR)

TCR selects the TCNT clock source and the condition by which TCNT is cleared, and
enables/disables interrupt requests.
Bit Bit Name
7 CMIEB
6 CMIEA
5 OVIE
4 CCLR1
3 CCLR0
2 CKS2
1 CKS1
0 CKS0
Rev. 1.00 Apr. 28, 2008 Page 362 of 994
REJ09B0452-0100
Initial
Value R/W Description
0 R/W Compare-Match Interrupt Enable B
Selects whether the CMFB interrupt request (CMIB) is
enabled or disabled when the CMFB flag in TCSR is
set to 1.
0: CMFB interrupt request (CMIB) is disabled
1: CMFB interrupt request (CMIB) is enabled
0 R/W Compare-Match Interrupt Enable A
Selects whether the CMFA interrupt request (CMIA) is
enabled or disabled when the CMFA flag in TCSR is
set to 1.
0: CMFA interrupt request (CMIA) is disabled
1: CMFA interrupt request (CMIA) is enabled
0 R/W Timer Overflow Interrupt Enable
Selects whether the OVF interrupt request (OVI) is
enabled or disabled when the OVF flag in TCSR is set
to 1.
0: OVF interrupt request (OVI) is disabled
1: OVF interrupt request (OVI) is enabled
0 R/W Counter Clear 1 and 0
0 R/W These bits select the method by which the timer
counter is cleared.
00: Clearing is disabled
01: Cleared on compare-match A
10: Cleared on compare-match B
11: Cleared on rising edge of external reset input
0 R/W Clock Select 2 to 0
0 R/W These bits select the clock input to TCNT and count
condition, together with the ICKS1 and ICKS0 bits in
0 R/W
STCR. For details, see table 13.3.