Operation; Timer Mode - Renesas H8S/2100 Series Hardware Manual

12.4

Operation

The TDP operates in timer mode or cycle measurement mode. After a reset, the TDP is in timer
mode.
12.4.1

Timer Mode

When the TDPMDS bit in TDPCR1 is cleared to 0, the TDP operates in timer mode.
(1) Counter Operation
The TDP operates as a free-running counter in timer mode. The TDP starts counting up when the
CST bit in TDPCR1 is set to 1. When TDPCNT overflows (H'FFFF changes to H'0000), the OVF
bit in TDPCSR is set to 1 and an interrupt request is generated if the OVIE bit in TDPIER is 1.
Figure 12.2 shows an example of free-running counter operation. In addition, figure 12.3 shows
TDPCNT count timing for external clock operation. Note that the external clock requires a pulse
width of at least 1.5 cycles. The counter will not operate correctly if the pulses are narrower than
this.
φ
φ/4
TDPCNT
input clock
TDPCNT
Figure 12.2 Example of Free-Running Counter Operation
φ
TDPCKI
TDPCNT
input clock
TDPCNT
Figure 12.3 Count Timing of External Clock Operation (Falling Edges)
Section 12 16-Bit Duty Period Measurement Timer (TDP)
N - 1
N - 1
N
N
Rev. 1.00 Apr. 28, 2008 Page 343 of 994
REJ09B0452-0100
N + 1
N + 1