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16.3.5
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the sampling clock signal used for CIR reception. The bit rate
for the CIR reception is determined by a combination of the setting value in BRR and the CLK1
and CLK0 bits in CCR1.
Bit
Bit Name
7 to 0
BRR7 to
BRR1
The following formula is used for calculating the bit rate, and the following table shows BRR
setting examples to obtain a target bit rate.
B = T / (N + 1)
B: Bit rate (bits/s)
T: Frequency of the reference clock (Hz) set by the CLK1 and CLK0 bits in CCR1 (φ, φ/2, φ/4, or
φsub)
N: Set value in BRR (0 ≤ N ≤ 255)
Table 16.3 Setting Example of BRR
Carrier
φ
Frequency
38kHz
20 MHz
10 MHz
8 MHz
Initial
Value
R/W
Description
All 1
R/W
Sets the value of the sampling clock.
CLK1 and
BRR Setting
CLK0 Setting
Value
φ
H'FF
φ/2
H'FF
φ/4
H'83
φ
H'FF
φ/2
H'83
φ/4
H'41
φ
H'D2
φ/2
H'69
φ/4
H'34
φsub
H'00
Section 16 CIR Interface
Deviation from
Bit Rate
Target Carrier
(Kbit/s)
Frequency
78.1
51.36%
39.1
2.72%
−0.32%
37.9
39.1
2.72%
−0.32%
37.9
−0.32%
37.9
−0.23%
37.9
−0.70%
37.7
−0.70%
37.7
32.8
2.34%
Rev. 1.00 Apr. 28, 2008 Page 477 of 994
REJ09B0452-0100
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