Usage Notes - Renesas H8S/2100 Series Hardware Manual

2
Section 18 I C Bus Interface (IIC)
18.6

Usage Notes

1. In master mode, if an instruction to generate a start condition is issued and then an instruction
to generate a stop condition is issued before the start condition is output to the I
condition will be output correctly.
2. Either of the following two conditions will start the next transfer. Pay attention to these
conditions when accessing ICDR.
 Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to
ICDRS)
 Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to
ICDRR)
3. Table 18.9 shows the timing of SCL and SDA outputs in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
2
Table 18.9 I C Bus Timing (SCL and SDA Outputs)
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
Data output hold time
Note: * 6t when IICX is 0, 12t
cyc
Rev. 1.00 Apr. 28, 2008 Page 582 of 994
REJ09B0452-0100
Symbol
t
SCLO
t
SCLHO
t
SCLLO
t
BUFO
t
STAHO
t
STASO
t
STOSO
t
SDASO
t
SDAHO
when 1.
cyc
Output Timing
28t to 256t
cyc cyc
0.5t
SCLO
0.5t
SCLO
0.5t – 1t
SCLO cyc
0.5t – 1t
SCLO cyc
1t
SCLO
0.5t + 2t
SCLO cyc
1t – 3t
SCLLO cyc
1t – (6t or
SCLL cyc
12t
*)
cyc
3t
cyc
2
C bus, neither
Unit Notes
ns See figure
28.24 (for
ns
reference)
ns
ns
ns
ns
ns
ns
ns