Interrupt Sources; Ibfi1, Ibfi2, Ibfi3, Ibfi4, Obei, And Erri - Renesas H8S/2100 Series Hardware Manual

Section 20 LPC Interface (LPC)
20.5

Interrupt Sources

20.5.1

IBFI1, IBFI2, IBFI3, IBFI4, OBEI, and ERRI

The host has six interrupt requests for the slave (this LSI): IBF1, IBF2, IBF3, IBF4, OBEI, and
ERRI. IBFI1, IBFI2, IBFI3, and IBFI4 are IDR receive complete interrupts for IDR1, IDR2, and
IDR3 and TWR, respectively. The ERRI interrupt indicates the occurrence of a special state such
as an LPC reset, LPC shutdown, or transfer cycle abort. The LMCI and LMCUI interrupts are
command receive complete interrupts. OBEI is an output buffer empty interrupt. An interrupt
request is enabled by setting the corresponding enable bit.
Table 20.9 Receive Complete Interrupts and Error Interrupt
Interrupt Description
IBFI1 When IBFIE1 is set to 1 and IDR1 reception is completed
IBFI2 When IBFIE2 is set to 1 and IDR2 reception is completed
IBFI3 When IBFIE3 is set to 1 and IDR3 reception is completed, or when TWRE and
IBFIE3 are set to 1 and reception is completed up to TWR15
IBFI4 When IBFIE4 is set to 1 and IDR4 reception is completed
OBEI When OBEIE is set to 1 with OBEI set to 1.
ERRI When ERRIE is set to 1 and one of LRST, SDWN and ABRT is set to 1
Rev. 1.00 Apr. 28, 2008 Page 674 of 994
REJ09B0452-0100