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11.4
Operation
The TCM operates in timer mode or cycle measurement mode. TCM is in timer mode after a reset.
11.4.1
Timer Mode
When the TCMMDS bit in TCMCR is cleared to 0, TCM operates in timer mode.
(1)
Counter Operation
TCMCNT operates as a free running counter in timer mode. TCMCNT starts counting up when
the CST bit in TCMCR is set to 1. When TCMCNT overflows (the value changes from H'FFFF to
H'0000), the OVF bit in TCMCSR is set to 1 and an interrupt request is generated if the OVIE bit
in TCMIER is 1. Figure 11.2 shows an example of free running counter operation. In addition,
figure 11.3 shows TCMCNT count timing of external clock operation. The external clock should
have a pulse width of no less than 1.5 cycles. The counter will not operate correctly if the pulses
are narrower than this.
φ
φ/4
TCMCNT
input clock
TCMCNT
Figure 11.2 Example of Free Running Counter Operation
φ
TCMCKI
TCMCNT
input clock
TCMCNT
Figure 11.3 Count Timing of External Clock Operation (Falling Edges)
Section 11 16-Bit Cycle Measurement Timer (TCM)
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Rev. 1.00 Apr. 28, 2008 Page 317 of 994
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