Input/Output Pins; Register Descriptions - Renesas H8S/2100 Series Hardware Manual

12.2

Input/Output Pins

Table 12.1 lists the pin configuration of the TDP.
Table 12.1 Pin Configuration
Channel Pin Name
0 TDPCKI0
(TDPMCI0)
TDPCYI0
1 TDPCKI1
(TDPMCI1)
TDPCYI1
2 TDPCKI2
(TDPMCI2)
TDPCYI2
12.3

Register Descriptions

The TDP has the following registers.
Table 12.2 Register Configuration
Channel Register Name
Channel 0 TDP timer counter_0
TDP pulse width upper limit register_0
TDP pulse width lower limit register_0
TDP cycle upper limit register_0
TDP cycle lower limit register_0
TDP input capture register_0
TDP input capture buffer register_0
TDP status register_0
TDP control register1_0
TDP control register2_0
TDP interrupt enable register_0
Section 12 16-Bit Duty Period Measurement Timer (TDP)
I/O Function
Input External counter clock input
Cycle measurement control input
Input External event input
Input External counter clock input
Cycle measurement control input
Input External event input
Input External counter clock input
Cycle measurement control input
Input External event input
Abbreviation
TDPCNT_0
TDPWDMX_0
TDPWDMN_0
TDPPDMX_0
TDPPDMN_0
TDPICR_0
TDPICRF_0
TDPCSR_0
TDPCR1_0
TDPCR2_0
TDPIER_0
Initial
R/W Value Address
R/W H'0000 H'FB40
R/W H'FFFF H'FB42
R/W H'0000 H'FB44
R/W H'FFFF H'FB46
R/W H'0000 H'FB50
R H'0000 H'FB48
R H'0000 H'FB4A
R/W H'00 H'FB4C
R/W H'00 H'FB4D
R/W H'00 H'FB4F
R/W H'00 H'FB4E
Rev. 1.00 Apr. 28, 2008 Page 331 of 994
REJ09B0452-0100
Data
Bus
Width
16
16
16
16
16
16
16
8
8
8
8