Operation; Lpc/Fw Memory Cycles - Renesas H8S/2100 Series Hardware Manual

21.4

Operation

21.4.1

LPC/FW Memory Cycles

In LPC/FW memory read and write cycles, data is transferred using LAD3 to LAD0
synchronously with LCLK. The order of data transfer is shown in table 21.4. In a cycle returning
synchronization signal from the slave, the slave usually returns B'1010 to notify the host of error
occurrence; while the FSI in this LSI always returns B'0000 (Ready) or B'0110 (Long wait).
The FSI becomes busy if the received address matches an address in the host accessible range set
in the registers (FSIHBARH, FSIHBARL, FSISR, and CMDHBAR), and outputs a turn-around
signal to return to the idle state.
Table 21.4 LPC Memory Read/Write Cycles
LPC Memory Read Cycles
State
Counts Content
1 Start
2 Cycle type/
direction
3 Address 1
4 Address 2
5 Address 3
6 Address 4
7 Address 5
8 Address 6
9 Address 7
10 Address 8
11 Turn-around
(recovery)
12 Turn-around None
13 Wait*
Driven by Value (3 to 0)
Host 0000
Host 0100
Host bit 31 to bit 28
Host bit 27 to bit 24
Host bit 23 to bit 20
Host bit 19 to bit 16
Host bit 15 to bit 12
Host bit 11 to bit 8
Host bit 7 to bit 4
Host bit 3 to bit 0
Host 1111
ZZZZ
Slave 0110
LPC Memory Write Cycles
Content Driven by
Start Host
Cycle type/ Host
direction
Address 1 Host
Address 2 Host
Address 3 Host
Address 4 Host
Address 5 Host
Address 6 Host
Address 7 Host
Address 8 Host
Data 1 Host
Data 2 Host
Turn-around Host
(recovery)
Rev. 1.00 Apr. 28, 2008 Page 703 of 994
Section 21 FSI Interface
Value (3 to 0)
0000
0110
bit 31 to bit 28
bit 27 to bit 24
bit 23 to bit 20
bit 19 to bit 16
bit 15 to bit 12
bit 11 to bit 8
bit 7 to bit 4
bit 3 to bit 0
bit 3 to bit 0
bit 7 to bit 4
1111
REJ09B0452-0100