Keyboard Buffer Control Register 2 (Kbcr2) - Renesas H8S/2100 Series Hardware Manual

19.3.2

Keyboard Buffer Control Register 2 (KBCR2)

KBCR2 is a 4-bit counter which performs counting synchronized with the falling edge of KCLK.
Transmit data is synchronized with the transmit counter, and data in the KBTR is sent to the KD
(LSB-first).
Bit Bit Name

7 to 4
3 TXCR3
2 TXCR2
1 TXCR1
0 TXCR0
Initial
Value R/W Description
All 1 R/W Reserved
These bits are always read as 0. The initial value
should not be changed.
0 R Transmit Counter
0 R Indicates bit of transmit data. Counter is incremented
at the falling edge of KCLK. The transmit counter is
0 R
initialized by a reset, when the KBTS is cleared to 0,
0 R
the KBIOE is cleared to 0, or the KBTE is set to 1.
0000: Clear
0001: KBT0
0010: KBT1
0011: KBT2
0100: KBT3
0101: KBT4
0110: KBT5
0111: KBT6
1000: KBT7
1001: Parity bit
1010: Stop bit
1011: Transmit completion notification
Section 19 Keyboard Buffer Control Unit (PS2)
Rev. 1.00 Apr. 28, 2008 Page 593 of 994
REJ09B0452-0100