Input/Output Pins - Renesas H8S/2100 Series Hardware Manual

20.2

Input/Output Pins

Table 20.1 lists the LPC pin configuration.
Table 20.1 Pin Configuration
Name Abbreviation
LPC address/ LAD3 to LAD0 P33 to P30 I/O
data 3 to 0
LFRAME
LPC frame
LRESET
LPC reset
LPC clock LCLK
Serialized SERIRQ
interrupt request
LSCI general LSCI
output
LSMI
LSMI general
output
PME
PME general
output
GATE A20 GA20
CLKRUN
LPC clock run
LPC power-down LPCPD
Notes: 1. Pin state monitoring input is possible in addition to the LPC interface control
input/output function.
2. Only 0 can be output. If 1 is output, the pin is in the high-impedance state, so an
external resistor is necessary to pull the signal up to VCC.
Port I/O
1
P34 Input*
1
P35 Input*
P36 Input
1
P37 I/O*
1,
PB1 Output*
1,
PB0 Output*
1,
P80 Output*
1,
P81 Output*
1, 2
P82 I/O* *
1
P83 Input*
Section 20 LPC Interface (LPC)
Function
Cycle type/address/data signals
serially (4-signal-line) transferred in
synchronization with LCLK
Transfer cycle start and forced
termination signal
LPC interface reset signal
33-MHz PCI clock signal
Serialized host interrupt request
signal in synchronization with LCLK
2
General output
*
2
General output
*
2
* General output
2
* Gate A20 control signal output
LCLK restart request signal when
serial host interrupt is requested
LPC module shutdown signal
Rev. 1.00 Apr. 28, 2008 Page 617 of 994
REJ09B0452-0100