Operation Of Fifo Register - Renesas H8S/2100 Series Hardware Manual

16-bit single-chip microcomputer
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Section 16 CIR Interface
16.4.2

Operation of FIFO Register

A FIFO structure provides first-in first-out operation.
Operation of the FIFO when it receives data three times (byte 0, byte 1, and byte 2 in order) and is
then read three times is as shown below.
Operation for first reception
of data
Number of bytes
Figure 16.6
First read
Number of bytes
FIFO Contents
1
Byte 1
2
Byte 2
H'00
3
4
H'00
.
.
.
18
H'00
Rev. 1.00 Apr. 28, 2008 Page 486 of 994
REJ09B0452-0100
FIFO contents
1
Byte 0
2
H'00
H'00
3
4
H'00
.
.
.
.
.
.
18
H'00
Operation when FIFO Data is Received
Second read
N
umber of bytes
.
.
.
Figure 16.7
Operation when FIFO Data is Read
Operation for data reception
three times
Number of bytes
1
2
3
4
.
.
.
18
FIFO Contents
1
Byte 2
2
H'00
H'00
3
4
H'00
.
.
.
.
.
.
18
H'00
FIFO contents
Byte 0
Byte 1
Byte 2
H'00
.
.
.
H'00
Third read
Number of bytes
FIFO contents
1
H'00
2
H'00
H'00
3
4
H'00
.
.
.
18
H'00
.
.
.

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