Operation; Pulse Output - Renesas H8S/2100 Series Hardware Manual

13.4

Operation

13.4.1

Pulse Output

Figure 13.3 shows an example for outputting an arbitrary duty pulse.
1. Clear the CCLR1 bit in TCR to 0, and set the CCLR0 bit in TCR to 1 so that TCNT is cleared
according to the compare match of TCORA.
2. Set the OS3 to OS0 bits in TCSR to B'0110 so that 1 is output according to the compare match
of TCORA and 0 is output according to the compare match of TCORB.
According to the above settings, the waveforms with the TCORA cycle and TCORB pulse width
can be output without the intervention of software.
H'FF
TCORA
TCORB
H'00
TMO
TCNT
Figure 13.3 Pulse Output Example
Section 13 8-Bit Timer (TMR)
Counter clear
Rev. 1.00 Apr. 28, 2008 Page 375 of 994
REJ09B0452-0100