Modem Control Register (Fmcr) - Renesas H8S/2100 Series Hardware Manual

Section 17 Serial Communication Interface with FIFO (SCIF)
Bit Bit Name
2 STOP
1 CLS1
0 CLS0

17.3.10 Modem Control Register (FMCR)

FMCR controls output signals.
Bit Bit Name

7 to 5
4 LOOP
BACK
Rev. 1.00 Apr. 28, 2008 Page 504 of 994
REJ09B0452-0100
Initial Value R/W
0 R/W
0 R/W
0 R/W
Initial Value R/W
All 0 R
0 R/W
Description
Stop Bit
Specifies the stop bit length for data transmission.
For data reception, only the first stop bit is checked
regardless of the setting.
0: 1 stop bit
1: 1.5 stop bits (data length: 5 bits) or 2 stop bits
(data length: 6 to 8 bits)
Character Length Select 1, 0
These bits specify transmit/receive character data
length.
00: Data length is 5 bits
01: Data length is 6 bits
10: Data length is 7 bits
11: Data length is 8 bits
Description
Reserved
These bits are always read as 1 and cannot be
modified.
Loopback Test
The transmit data output is internally connected to
the receive data input, and the transmit data output
pin (FRxD) becomes 1. The receive data input pin is
disconnected from external sources. The four modem
control input pins (DSR, CTS, RI, and DCD) are
disconnected from external sources, and the pins are
internally connected to the four modem control output
signals (DTR, RTS, OUT1, and OUT2), respectively.
The transmit data is received immediately in
loopback mode. Enabling/disabling of interrupts is set
by the OUT2LOOP bit in SCIFCR and FIER.
0: Loopback function disabled
1: Loopback function enabled