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12.6.5
Conflict between Edge Detection in Cycle Measurement Mode and TDPMDS Bit
Clearing
When the TDPMDS bit in TDPCR1 is cleared in cycle measurement mode while the CST bit in
TDPCR1 is 1 and the edge of TDPCYI is detected at the same time, the detected edge signal will
cause the timer to continue to operate in cycle measurement mode. The timer enters timer mode
when the next edge is detected. Therefore, ensure that the CST bit is cleared to 0 in cycle
measurement mode.
Figure 12.17 shows the timing of this conflict.
φ
TDPCYI
Input capture
signal
Internal write
signal
TDPMDS
TDPCNT
TDPICR
Figure 12.17 Conflict between Edge Detection and TDPMDS Bit Clearing (In Switching
12.6.6
Settings for TDPCKI and TDPMCI
TDPCKI and TDPMCI are multiplexed on the same pin of this LSI. Therefore, the selected
external clock and the TDPMCI signal cannot be used at the same time. Do not make the settings
CKS2 to CKS0 = B'111 and PMMS = B'1.
12.6.7
Setting for Module Stop Mode
The module-stop control register can be used to specify whether to continue or stop TDP
operation. The default setting is for the TDP operation to stop. The TDP registers become
accessible on release from module stop mode. For details, see section 26, Power-Down Modes.
TDPCNT cleared
at the first rising edge
M
H'0000
L
from Cycle Measurement Mode to Timer Mode)
Section 12 16-Bit Duty Period Measurement Timer (TDP)
N
M
Rev. 1.00 Apr. 28, 2008 Page 353 of 994
TDPCNT is not cleared
N + 1
N
REJ09B0452-0100
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