Timer Counter (Tcnt); Timer Control/Status Register (Tcsr) - Renesas H8S/2100 Series Hardware Manual

Section 14 Watchdog Timer (WDT)
14.3.1

Timer Counter (TCNT)

TCNT is an 8-bit readable/writable up-counter.
TCNT is initialized to H'00 when the TME bit in timer control/status register (TCSR) is cleared to
0.
14.3.2

Timer Control/Status Register (TCSR)

TCSR selects the clock source to be input to TCNT, and the timer mode.
• TCSR_0
Bit Bit Name
7 OVF
6 WT/IT
5 TME

4
Rev. 1.00 Apr. 28, 2008 Page 394 of 994
REJ09B0452-0100
Initial
Value R/W Description
0 R/(W)* Overflow Flag
Indicates that TCNT has overflowed (changes from
H'FF to H'00).
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in
watchdog timer mode, OVF is cleared automatically by
the internal reset.
[Clearing conditions]
•
•
0 R/W Timer Mode Select
Selects whether the WDT is used as a watchdog timer
or interval timer.
0: Interval timer mode
1: Watchdog timer mode
0 R/W Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00.
0 R/(W) Reserved
The initial value should not be changed.
When TCSR is read when OVF = 1, then 0 is written
to OVF
When 0 is written to TME